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/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dmatching-binops.ll19 ; CHECK-NEXT: [[A:%.*]] = and i8 [[SX]], [[Z:%.*]]
34 ; CHECK-NEXT: [[A:%.*]] = or i8 [[SX]], [[Z:%.*]]
49 ; CHECK-NEXT: [[A:%.*]] = xor i8 [[SX]], [[Z:%.*]]
64 ; CHECK-NEXT: [[A:%.*]] = and i8 [[SX]], [[Z:%.*]]
79 ; CHECK-NEXT: [[A:%.*]] = or i8 [[SX]], [[Z:%.*]]
94 ; CHECK-NEXT: [[A:%.*]] = xor i8 [[SX]], [[Z:%.*]]
109 ; CHECK-NEXT: [[A:%.*]] = and i8 [[SX]], [[Z:%.*]]
124 ; CHECK-NEXT: [[A:%.*]] = or i8 [[SX]], [[Z:%.*]]
158 ; CHECK-NEXT: [[A:%.*]] = or i8 [[SX]], [[Z:%.*]]
175 ; CHECK-NEXT: [[A:%.*]] = or i8 [[SX]], [[Z:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.round.ll7 ; GCN-DAG: s_load_dword [[SX:s[0-9]+]]
9 ; GCN-DAG: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[SX]]
10 ; GCN-DAG: v_sub_f32_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]]
11 ; GCN-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]]
63 ; GFX89-DAG: s_load_dword [[SX:s[0-9]+]]
65 ; GFX89-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]]
69 ; GFX89: v_trunc_f16_e32 [[TRUNC:v[0-9]+]], [[SX]]
70 ; GFX89: v_sub_f16_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]]
H A Dllvm.amdgcn.cvt.pk.i16.ll7 ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
9 ; SI: v_cvt_pk_i16_i32_e32 v{{[0-9]+}}, s[[SX]], [[VY]]
10 ; VI: v_cvt_pk_i16_i32 v{{[0-9]+}}, s[[SX]], [[VY]]
H A Dllvm.amdgcn.cvt.pk.u16.ll7 ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
9 ; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, s[[SX]], [[VY]]
10 ; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, s[[SX]], [[VY]]
H A Dllvm.amdgcn.cvt.pknorm.i16.ll7 ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
9 ; SI: v_cvt_pknorm_i16_f32_e32 v{{[0-9]+}}, s[[SX]], [[VY]]
10 ; VI: v_cvt_pknorm_i16_f32 v{{[0-9]+}}, s[[SX]], [[VY]]
H A Dllvm.amdgcn.cvt.pknorm.u16.ll7 ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
9 ; SI: v_cvt_pknorm_u16_f32_e32 v{{[0-9]+}}, s[[SX]], [[VY]]
10 ; VI: v_cvt_pknorm_u16_f32 v{{[0-9]+}}, s[[SX]], [[VY]]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.td127 def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)],
139 [!cast<VEReg>("SX"#!shl(I,1)),
140 !cast<VEReg>("SX"#!add(!shl(I,1),1))],
175 (add (sequence "SX%u", 0, 7),
176 (sequence "SX%u", 34, 63),
177 (sequence "SX%u", 8, 33))>;
H A DVECallingConv.td147 def CSR : CalleeSavedRegs<(add (sequence "SX%u", 18, 33))>;
151 def CSR_preserve_all : CalleeSavedRegs<(add (sequence "SX%u", 0, 61),
H A DVEInstrFormats.td9 // SX-Aurora uses little endian, but instructions are encoded little bit
/llvm-project-15.0.7/lldb/test/Shell/ObjectFile/ELF/
H A Deh_frame-symbols.yaml6 # CHECK: [ 1] 2 SX Code 0x0000000000201180 0x000000000000001…
7 # CHECK: [ 2] 3 SX Code 0x0000000000201190 0x000000000000000…
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td322 // A SX pipeline may take from 0 to 3 cycles to complete.
391 // Save 1 cycles if pipeline F2 reads the data from pipelines ST, SX, FX, F2, PM.
394 // Save 1 cycles if pipeline FX reads the data from pipelines ST, SX, FX, F2, PM.
397 // Save 1 cycles if pipeline LD reads the data from pipelines ST, SX, FX, F2.
403 // Save 1 cycles if pipeline PM reads the data from pipelines ST, SX, FX, F2, PM.
406 // Save 1 cycles if pipeline ST reads the data from pipelines ST, SX, FX, F2, PM.
409 // Save 1 cycles if pipeline SX reads the data from pipelines ST, SX, FX, F2, PM, MM.
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A D2004-11-27-SetCCForCastLargerAndConstant.ll406 ; CHECK-NEXT: [[SX:%.*]] = sext i7 [[X:%.*]] to i25
408 ; CHECK-NEXT: [[R:%.*]] = icmp ne i25 [[SX]], [[ZY]]
436 ; CHECK-NEXT: [[SX:%.*]] = sext i7 [[X:%.*]] to i25
437 ; CHECK-NEXT: call void @use(i25 [[SX]])
453 ; CHECK-NEXT: [[SX:%.*]] = sext i7 [[X:%.*]] to i25
454 ; CHECK-NEXT: call void @use(i25 [[SX]])
457 ; CHECK-NEXT: [[R:%.*]] = icmp ule i25 [[SX]], [[SY]]
H A Dmul.ll270 ; CHECK-NEXT: [[SX:%.*]] = sext i1 [[X:%.*]] to i32
271 ; CHECK-NEXT: call void @use32(i32 [[SX]])
274 ; CHECK-NEXT: [[R:%.*]] = mul nsw i32 [[SY]], [[SX]]
331 ; CHECK-NEXT: [[SX:%.*]] = sext i1 [[X:%.*]] to i32
332 ; CHECK-NEXT: call void @use32(i32 [[SX]])
344 ; CHECK-NEXT: [[SX:%.*]] = zext i1 [[X:%.*]] to i32
345 ; CHECK-NEXT: call void @use32(i32 [[SX]])
399 ; CHECK-NEXT: [[SX:%.*]] = sext i1 [[X:%.*]] to i32
400 ; CHECK-NEXT: call void @use32(i32 [[SX]])
403 ; CHECK-NEXT: [[R:%.*]] = select i1 [[Y]], i32 [[SX]], i32 0
H A Dand-xor-or.ll360 ; CHECK-NEXT: [[A:%.*]] = and i8 [[SX]], [[Z]]
376 ; CHECK-NEXT: [[A:%.*]] = or i8 [[SX]], [[Z]]
393 ; CHECK-NEXT: [[A:%.*]] = xor i8 [[Z]], [[SX]]
428 ; CHECK-NEXT: [[A:%.*]] = or i8 [[SX]], [[Z]]
479 ; CHECK-NEXT: [[A:%.*]] = or i8 [[Z]], [[SX]]
514 ; CHECK-NEXT: [[A:%.*]] = or i8 [[SX]], [[Z]]
532 ; CHECK-NEXT: [[A:%.*]] = or i8 [[SX]], [[Z]]
548 ; CHECK-NEXT: [[SX:%.*]] = lshr i8 [[X]], 5
550 ; CHECK-NEXT: [[A:%.*]] = or i8 [[SX]], [[Z]]
4177 ; CHECK-NEXT: call void @use(i32 [[SX]])
[all …]
H A Dmul-inseltpoison.ll235 ; CHECK-NEXT: [[SX:%.*]] = sext i1 [[X:%.*]] to i32
236 ; CHECK-NEXT: call void @use32(i32 [[SX]])
239 ; CHECK-NEXT: [[R:%.*]] = mul nsw i32 [[SY]], [[SX]]
294 ; CHECK-NEXT: [[SX:%.*]] = sext i1 [[X:%.*]] to i32
295 ; CHECK-NEXT: call void @use32(i32 [[SX]])
298 ; CHECK-NEXT: [[R:%.*]] = select i1 [[Y]], i32 [[SX]], i32 0
H A Dminmax-intrinsics.ll88 ; CHECK-NEXT: [[SX:%.*]] = sext i5 [[X:%.*]] to i8
89 ; CHECK-NEXT: call void @use(i8 [[SX]])
186 ; CHECK-NEXT: [[SX:%.*]] = sext i5 [[X:%.*]] to i8
188 ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.umin.i8(i8 [[SX]], i8 [[ZY]])
2380 ; CHECK-NEXT: call void @use_vec(<3 x i8> [[SX]])
2423 ; CHECK-NEXT: [[SX:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> poison, <3 x i32> <i32 0, …
2424 ; CHECK-NEXT: [[R:%.*]] = call <3 x i8> @llvm.smax.v3i8(<3 x i8> [[SX]], <3 x i8> [[Y:%.*]])
2438 ; CHECK-NEXT: [[R:%.*]] = call <3 x i8> @llvm.smax.v3i8(<3 x i8> [[SX]], <3 x i8> [[SY]])
2453 ; CHECK-NEXT: [[R:%.*]] = call <3 x i8> @llvm.smax.v3i8(<3 x i8> [[SX]], <3 x i8> [[SY]])
2467 ; CHECK-NEXT: call void @use_vec(<3 x i8> [[SX]])
[all …]
H A Dicmp-range.ll516 ; CHECK-NEXT: [[SX:%.*]] = sext i4 [[X:%.*]] to i8
517 ; CHECK-NEXT: call void @use(i8 [[SX]])
/llvm-project-15.0.7/llvm/cmake/
H A Dconfig.guess1232 SX-4:SUPER-UX:*:*)
1235 SX-5:SUPER-UX:*:*)
1238 SX-6:SUPER-UX:*:*)
1241 SX-7:SUPER-UX:*:*)
1244 SX-8:SUPER-UX:*:*)
1247 SX-8R:SUPER-UX:*:*)
/llvm-project-15.0.7/lldb/test/Shell/SymbolFile/Breakpad/
H A Dsymtab.test8 # CHECK: [ 0] 0 SX Code 0x0000000000400000 0x00000000000000b…
/llvm-project-15.0.7/openmp/libomptarget/plugins/ve/
H A DCMakeLists.txt9 libomptarget_say("Building SX-Aurora VE offloading plugin.")
/llvm-project-15.0.7/llvm/docs/Proposals/
H A DVectorPredication.rst16 extension and NEC SX-Aurora. Only some predicated vector operations, such as
/llvm-project-15.0.7/llvm/docs/
H A DCompilerWriterInfo.rst130 * `NEC SX-Aurora TSUBASA ISA Guide <https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf>`_
131 * `NEC SX-Aurora TSUBASA manuals and documentation <https://www.hpc.nec/documentation>`_
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SchedSkylakeClient.td1129 def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
1130 "(V?)PMOV(SX|ZX)BQrm",
1131 "(V?)PMOV(SX|ZX)BWrm",
1132 "(V?)PMOV(SX|ZX)DQrm",
1133 "(V?)PMOV(SX|ZX)WDrm",
1134 "(V?)PMOV(SX|ZX)WQrm")>;
H A DX86SchedHaswell.td1008 def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm",
1009 "(V?)PMOV(SX|ZX)BQrm",
1010 "(V?)PMOV(SX|ZX)BWrm",
1011 "(V?)PMOV(SX|ZX)DQrm",
1012 "(V?)PMOV(SX|ZX)WDrm",
1013 "(V?)PMOV(SX|ZX)WQrm")>;
H A DX86SchedSkylakeServer.td1312 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
1313 "(V?)PMOV(SX|ZX)BQrm",
1314 "(V?)PMOV(SX|ZX)BWrm",
1315 "(V?)PMOV(SX|ZX)DQrm",
1316 "(V?)PMOV(SX|ZX)WDrm",
1317 "(V?)PMOV(SX|ZX)WQrm")>;

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