Searched refs:SWR (Results 1 – 13 of 13) sorted by relevance
| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/ |
| H A D | unaligned-memops.ll | 18 ; MIPS: SWR [[LWR]], [[COPY]], 3 :: (store (s32) into %ir.b, align 1)
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| H A D | unaligned-memops-mapping.mir | 63 SWR %4, %1, 3 :: (store (s32) into %ir.b, align 1)
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| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| H A D | store_4_unaligned.mir | 45 ; MIPS32: SWR [[COPY1]], [[ADDiu]], 0 :: (store (s32) into @float_align1, align 1)
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 241 case Mips::SWR: in isBasePlusOffsetMemoryAccess()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrHFP.td | 164 def SWR : BinaryRR<"swr", 0x2F, null_frag, FP64, FP64>;
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenSchedule.cpp | 1914 for (Record *SWR : SWRDefs) { in collectProcResources() 1915 Record *ModelDef = SWR->getValueAsDef("SchedModel"); in collectProcResources() 1916 addWriteRes(SWR, getProcModel(ModelDef).Index); in collectProcResources()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 251 SWR, enumerator
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| H A D | MipsInstructionSelector.cpp | 473 if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO)) in select()
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| H A D | MipsISelLowering.cpp | 216 case MipsISD::SWR: return "MipsISD::SWR"; in getTargetNodeName() 2774 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); in lowerUnalignedIntStore() 4930 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) in emitSTR_W() 5014 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) in emitSTR_D() 5022 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) in emitSTR_D()
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| H A D | MipsScheduleP5600.td | 144 SBE, SHE, SWE, SCE, SWL, SWR, SWLE, SWRE)>;
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| H A D | MipsScheduleGeneric.td | 576 def : InstRW<[GenericWriteStore], (instrs SWL, SWR)>;
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| H A D | MipsInstrInfo.td | 144 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 2132 def SWR : MMRel, StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4520 unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR; in expandUxw()
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