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/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dverify-liveness-at-def.mir38 # CHECK-SUB-NOT: Bad machine code
42 # CHECK-SUB: v. register: %0
43 # CHECK-SUB: lanemask: 0000000000000002
45 # CHECK-SUB-NOT: Bad machine code
48 # CHECK-SUB-NEXT: function: test_fail
49 # CHECK-SUB: v. register: %1
52 # CHECK-SUB-NOT: Bad machine code
55 # CHECK-SUB-NEXT: function: test_fail
56 # CHECK-SUB: v. register: %1
60 # CHECK-SUB-NEXT: function: test_fail
[all …]
/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/
H A Dpre-process.ll.expected5 ; RUN: | FileCheck %s --check-prefix=CHECK-SUB
16 ; CHECK-SUB-LABEL: test_add_constant:
17 ; CHECK-SUB: # %bb.0: # %entry
18 ; CHECK-SUB-NEXT: leaq -6(%rdi), %rax
19 ; CHECK-SUB-NEXT: retq
21 ; CHECK-SUB-I16-LABEL: test_add_constant:
22 ; CHECK-SUB-I16: # %bb.0: # %entry
23 ; CHECK-SUB-I16-NEXT: # kill: def $edi killed $edi def $rdi
24 ; CHECK-SUB-I16-NEXT: leal -6(%rdi), %eax
25 ; CHECK-SUB-I16-NEXT: # kill: def $ax killed $ax killed $eax
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsub-or-and-xor.ll9 ; CHECK-NEXT: ret i32 [[SUB]]
20 ; CHECK-NEXT: call void @use(i32 [[SUB]])
21 ; CHECK-NEXT: ret i32 [[SUB]]
34 ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[X]], [[Y]]
35 ; CHECK-NEXT: ret i32 [[SUB]]
48 ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[X]], [[Y]]
49 ; CHECK-NEXT: ret i32 [[SUB]]
61 ; CHECK-NEXT: ret i32 [[SUB]]
72 ; CHECK-NEXT: ret i32 [[SUB]]
83 ; CHECK-NEXT: ret <2 x i32> [[SUB]]
[all …]
H A Dsub-xor-or-neg-and.ll9 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
10 ; CHECK-NEXT: ret i32 [[SUB]]
21 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
22 ; CHECK-NEXT: call void @use(i32 [[SUB]])
23 ; CHECK-NEXT: ret i32 [[SUB]]
38 ; CHECK-NEXT: ret i32 [[SUB]]
53 ; CHECK-NEXT: ret i32 [[SUB]]
66 ; CHECK-NEXT: ret i32 [[SUB]]
78 ; CHECK-NEXT: ret i32 [[SUB]]
90 ; CHECK-NEXT: ret <2 x i32> [[SUB]]
[all …]
H A Dsub-and-or-neg-xor.ll9 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
10 ; CHECK-NEXT: ret i32 [[SUB]]
21 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
22 ; CHECK-NEXT: call void @use(i32 [[SUB]])
23 ; CHECK-NEXT: ret i32 [[SUB]]
38 ; CHECK-NEXT: ret i32 [[SUB]]
53 ; CHECK-NEXT: ret i32 [[SUB]]
66 ; CHECK-NEXT: ret i32 [[SUB]]
78 ; CHECK-NEXT: ret i32 [[SUB]]
90 ; CHECK-NEXT: ret <2 x i32> [[SUB]]
[all …]
H A Dbinop-select.ll9 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
24 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
39 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
40 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 1
54 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
95 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]
125 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[COND]]
126 ; CHECK-NEXT: ret i32 [[SUB]]
178 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[COND]]
179 ; CHECK-NEXT: ret i32 [[SUB]]
[all …]
H A Dzext-bool-add-sub.ll142 ; CHECK-NEXT: ret i64 [[SUB]]
154 ; CHECK-NEXT: ret i64 [[SUB]]
165 ; CHECK-NEXT: ret <2 x i64> [[SUB]]
175 ; CHECK-NEXT: ret <2 x i64> [[SUB]]
228 ; CHECK-NEXT: ret i64 [[SUB]]
240 ; CHECK-NEXT: ret i64 [[SUB]]
251 ; CHECK-NEXT: ret <2 x i64> [[SUB]]
272 ; CHECK-NEXT: ret i8 [[SUB]]
285 ; CHECK-NEXT: ret <2 x i8> [[SUB]]
298 ; CHECK-NEXT: ret <2 x i8> [[SUB]]
[all …]
H A Dunsigned_saturated_sub.ll41 ; CHECK-NEXT: call void @use(i64 [[SUB]])
68 ; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[A]], [[B]]
70 ; CHECK-NEXT: call void @use(i64 [[SUB]])
210 ; CHECK-NEXT: call void @use(i64 [[SUB]])
225 ; CHECK-NEXT: call void @use(i64 [[SUB]])
269 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[A]], -1
329 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[A]], -2
383 ; CHECK-NEXT: call void @usei32(i32 [[SUB]])
396 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[A]], -2
409 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[A]], -2
[all …]
/llvm-project-15.0.7/clang/test/Index/
H A Dcomplete-ivar-access.m53 …ex-test -code-completion-at=%s:43:8 -fobjc-nonfragile-abi %s | FileCheck -check-prefix=CHECK-SUB %s
54 …ex-test -code-completion-at=%s:48:8 -fobjc-nonfragile-abi %s | FileCheck -check-prefix=CHECK-SUB %s
55 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText sub_private} (35)
56 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText sub_protected} (35)
57 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText sub_public} (35)
58 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_ext_private} (35) (inaccessible)
59 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_ext_protected} (35)
60 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_ext_public} (35)
61 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_private} (37) (inaccessible)
62 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_protected} (37)
[all …]
/llvm-project-15.0.7/lld/test/MachO/
H A Dweak-definition-gc.s13 # RUN: llvm-otool -jtV %t/out.dylib | FileCheck --check-prefix=SUB %s
15 # RUN: llvm-otool -jtV %t/out.dylib | FileCheck --check-prefix=SUB %s
17 # RUN: llvm-otool -jtV %t/out.dylib | FileCheck --check-prefix=SUB %s
18 # SUB: _foo
19 # SUB-NEXT: retq
20 # SUB-NOT: retq
21 # SUB: _bar
22 # SUB-NEXT: retq
23 # SUB-NOT: retq
28 # RUN: llvm-otool -jtV %t/out.dylib | FileCheck --check-prefix=SUB %s
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dbfe-patterns.ll49 ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
50 ; GCN: s_lshl_b32 [[TMP:s[0-9]+]], s[[SRC]], [[SUB]]
51 ; GCN: s_lshr_b32 s{{[0-9]+}}, [[TMP]], [[SUB]]
64 ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
65 ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], s[[SRC]], [[SUB]]
66 ; GCN: s_lshr_b32 s{{[0-9]+}}, [[SHL]], [[SUB]]
123 ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
124 ; GCN: s_lshl_b32 [[TMP:s[0-9]+]], s[[SRC]], [[SUB]]
125 ; GCN: s_ashr_i32 s{{[0-9]+}}, [[TMP]], [[SUB]]
138 ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Dreplace-loop-exit-folds.ll16 ; CHECK-NEXT: [[SIZE_ADDR_0:%.*]] = phi i32 [ [[SIZE]], [[ENTRY:%.*]] ], [ [[SUB:%.*]], [[WHILE_…
18 ; CHECK-NEXT: [[SUB]] = add i32 [[SIZE_ADDR_0]], -32
46 ; CHECK-NEXT: [[SUB]] = add i32 [[SIZE_ADDR_0]], -32
77 ; CHECK-NEXT: [[SUB]] = add nsw i32 [[S_ADDR_0]], -32
108 ; CHECK-NEXT: [[SUB]] = add nsw i32 [[S_ADDR_0]], -16
110 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[SUB]], 15
113 ; CHECK-NEXT: [[SUB_LCSSA:%.*]] = phi i32 [ [[SUB]], [[DO_BODY]] ]
140 ; CHECK-NEXT: [[SUB]] = add i32 [[S_ADDR_0]], -16
171 ; CHECK-NEXT: [[SUB]] = add i32 [[S_ADDR_0]], -16
173 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[SUB]], 15
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dlegalize-sub-v128.mir41 ; ALL: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[DEF1]]
42 ; ALL: $xmm0 = COPY [[SUB]](<16 x s8>)
67 ; ALL: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[DEF1]]
68 ; ALL: $xmm0 = COPY [[SUB]](<8 x s16>)
93 ; ALL: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[DEF1]]
94 ; ALL: $xmm0 = COPY [[SUB]](<4 x s32>)
119 ; ALL: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[DEF1]]
120 ; ALL: $xmm0 = COPY [[SUB]](<2 x s64>)
H A Dlegalize-sub-v512.mir42 ; ALL: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[DEF]], [[DEF1]]
43 ; ALL: $zmm0 = COPY [[SUB]](<64 x s8>)
68 ; ALL: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[DEF]], [[DEF1]]
69 ; ALL: $zmm0 = COPY [[SUB]](<32 x s16>)
94 ; ALL: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
95 ; ALL: $zmm0 = COPY [[SUB]](<16 x s32>)
120 ; ALL: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
121 ; ALL: $zmm0 = COPY [[SUB]](<8 x s64>)
H A Dlegalize-sub-v256.mir42 ; ALL: [[SUB:%[0-9]+]]:_(<32 x s8>) = G_SUB [[DEF]], [[DEF1]]
43 ; ALL: $ymm0 = COPY [[SUB]](<32 x s8>)
68 ; ALL: [[SUB:%[0-9]+]]:_(<16 x s16>) = G_SUB [[DEF]], [[DEF1]]
69 ; ALL: $ymm0 = COPY [[SUB]](<16 x s16>)
94 ; ALL: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[DEF]], [[DEF1]]
95 ; ALL: $ymm0 = COPY [[SUB]](<8 x s32>)
120 ; ALL: [[SUB:%[0-9]+]]:_(<4 x s64>) = G_SUB [[DEF]], [[DEF1]]
121 ; ALL: $ymm0 = COPY [[SUB]](<4 x s64>)
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-sub.mir20 ; GFX6-NEXT: $vgpr0 = COPY [[SUB]](s32)
27 ; GFX8-NEXT: $vgpr0 = COPY [[SUB]](s32)
34 ; GFX9-NEXT: $vgpr0 = COPY [[SUB]](s32)
54 ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV]], [[UV2]]
65 ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV]], [[UV2]]
99 ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
183 ; GFX9-NEXT: $vgpr0 = COPY [[SUB]](<2 x s16>)
427 ; GFX6-NEXT: $vgpr0 = COPY [[SUB]](s32)
469 ; GFX6-NEXT: $vgpr0 = COPY [[SUB]](s32)
476 ; GFX8-NEXT: $vgpr0 = COPY [[SUB]](s32)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-usub-sat.mir82 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
83 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
84 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
88 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
120 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
121 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
122 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
126 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
158 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
159 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
[all …]
H A Dlegalize-rem.mir12 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[MUL]]
13 ; CHECK-NEXT: $x0 = COPY [[SUB]](s64)
31 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[MUL]]
32 ; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
57 ; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
81 ; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
106 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL]]
107 ; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
165 ; CHECK-NEXT: $d0 = COPY [[SUB]](<2 x s32>)
188 ; CHECK-NEXT: $q0 = COPY [[SUB]](<4 x s32>)
[all …]
H A Dlegalize-ssubsat.mir75 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
76 ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
78 ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
112 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
113 ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 1
115 ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 1
148 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
149 ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 3
151 ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 3
186 ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 36
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h25 SUB = 0x02, enumerator
82 case SUB: in lanaiAluCodeToString()
107 .Case("sub", SUB) in stringToLanaiAluCode()
124 case ISD::SUB: in isdToLanaiAluCode()
125 return AluCode::SUB; in isdToLanaiAluCode()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dsub.mir28 ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
29 ; MIPS32: $v0 = COPY [[SUB]](s32)
50 ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
52 ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
78 ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
80 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
106 ; MIPS32: $v0 = COPY [[SUB]](s32)
160 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
186 ; MIPS32: $v0 = COPY [[SUB]](s32)
219 ; MIPS32: $v1 = COPY [[SUB]](s32)
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ValueTracking/
H A Dnumsignbits-from-assume.ll36 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 1, [[IN:%.*]]
37 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
39 ; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
51 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[IN:%.*]], -1
52 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
54 ; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
66 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[IN1:%.*]], [[IN2:%.*]]
67 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
69 ; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
/llvm-project-15.0.7/llvm/test/Transforms/LoopDeletion/
H A Deval_first_iteration.ll296 ; CHECK-NEXT: [[MERGE_PHI:%.*]] = phi i32 [ 0, [[IF_FALSE]] ], [ [[SUB]], [[IF_TRUE]] ], [ [[SUB…
347 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 4, [[SUM]]
396 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 4, [[SUM]]
445 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 4, [[SUM]]
494 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 4, [[SUM]]
543 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 4, [[SUM]]
592 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 4, [[SUM]]
603 ; CHECK-NEXT: [[MERGE_PHI:%.*]] = phi i32 [ 0, [[IF_FALSE]] ], [ [[SUB]], [[IF_TRUE]] ], [ [[SUB…
652 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 4, [[SUM]]
726 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 4, [[SUM]]
[all …]
/llvm-project-15.0.7/clang/test/Preprocessor/
H A Dpragma-missing-string-token.c18 #define SUB "mypragma" macro
23 _Pragma(SUB);
24 int a = TEST(SUB);
/llvm-project-15.0.7/llvm/test/Instrumentation/AddressSanitizer/
H A Dasan-detect-invalid-pointer-pair.ll4 ; RUN: | FileCheck %s --check-prefixes=SUB,NOCMP,ALL
6 ; RUN: | FileCheck %s --check-prefixes=CMP,SUB,ALL
25 ; SUB: [[P:%[0-9A-Za-z]+]] = ptrtoint i8* %p to i64
26 ; SUB: [[Q:%[0-9A-Za-z]+]] = ptrtoint i8* %q to i64
30 ; SUB: call void @__sanitizer_ptr_sub(i64 [[P]], i64 [[Q]])

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