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Searched refs:STRD (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dintrinsics-memory-barrier.ll14 ; Failure to do so, two STRs will collapse into one STRD.
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dmemory-arm-instructions.txt389 # STRD (immediate)
409 # FIXME: STRD (label)
413 # STRD (register)
H A Dthumb2.txt1929 # STRD (immediate)
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA57.td614 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg.
624 def : InstRW<[A57WriteStrAm3X2], (instregex "STRD$")>;
650 // pre-indexed STRH/STRD (STRH_PRE, STRD_PRE)
682 // post-indexed STRH/STRD(STRH_POST, STRD_POST), STRHTi, STRHTr
H A DARMLoadStoreOptimizer.cpp222 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
1766 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8) in FixInvalidRegPairOp()
1781 bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) && in FixInvalidRegPairOp()
2270 NewOpc = ARM::STRD; in CanFormLdStDWord()
H A DARMISelLowering.h360 STRD enumerator
H A DARMScheduleR52.td501 (instregex "STRD$", "t2STRDi8", "STL", "t2STL")>;
H A DARMScheduleSwift.td502 (instregex "STRD$", "t2STRDi8")>;
H A DARMBaseInstrInfo.cpp1172 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD)); in storeRegToStackSlot()
3593 case ARM::STRD: { in getNumMicroOpsSwiftLdSt()
H A DARMExpandPseudoInsts.cpp3122 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD)) in ExpandMI()
H A DARMInstrInfo.td252 def ARMstrd : SDNode<"ARMISD::STRD", SDT_ARMstrd, [SDNPHasChain, SDNPMayStore, SDNPMemOpera…
3123 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
H A DARMISelDAGToDAG.cpp4058 case ARMISD::STRD: { in Select()
H A DARMISelLowering.cpp1724 MAKE_CASE(ARMISD::STRD) in getTargetNodeName()
10086 return DAG.getMemIntrinsicNode(ARMISD::STRD, dl, DAG.getVTList(MVT::Other), in LowerSTORE()
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2223 case ARM::STRD: in DecodeAddrMode3Instruction()
2235 case ARM::STRD: in DecodeAddrMode3Instruction()
2322 case ARM::STRD: in DecodeAddrMode3Instruction()
2339 case ARM::STRD: in DecodeAddrMode3Instruction()
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dbasic-thumb2-instructions.s3106 @ STRD
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td3308 defm STRD : Store64RO<0b11, 1, 0b00, FPR64Op, "str", f64, store>;
3426 defm STRD : StoreUI<0b11, 1, 0b00, FPR64Op, uimm12s8, "str",
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7764 case ARM::STRD: in validateInstruction()