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/llvm-project-15.0.7/llvm/test/Instrumentation/AddressSanitizer/
H A Dasan-optimize-callbacks.ll56 ; STORE-NEXT: store i8 0, i8* %p1, align 1
57 ; STORE-NEXT: %1 = bitcast i16* %p2 to i8*
59 ; STORE-NEXT: store i16 0, i16* %p2, align 2
60 ; STORE-NEXT: %2 = bitcast i32* %p4 to i8*
62 ; STORE-NEXT: store i32 0, i32* %p4, align 4
63 ; STORE-NEXT: %3 = bitcast i64* %p8 to i8*
65 ; STORE-NEXT: store i64 0, i64* %p8, align 8
66 ; STORE-NEXT: %4 = bitcast i128* %p16 to i8*
68 ; STORE-NEXT: store i128 0, i128* %p16, align 16
71 ; STORE-KERNEL-NEXT: store i8 0, i8* %p1, align 1
[all …]
H A Dasan-masked-load-store.ll17 ;;;;;;;;;;;;;;;; STORE
78 ; STORE: [[THEN0]]:
82 ; STORE: br label %[[AFTER0]]
83 ; STORE: [[AFTER0]]:
87 ; STORE: [[THEN1]]:
91 ; STORE: br label %[[AFTER1]]
92 ; STORE: [[AFTER1]]:
96 ; STORE: [[THEN2]]:
101 ; STORE: [[AFTER2]]:
105 ; STORE: [[THEN3]]:
[all …]
/llvm-project-15.0.7/llvm/test/Instrumentation/HeapProfiler/
H A Dmasked-load-store.ll17 ;;;;;;;;;;;;;;;; STORE
78 ; STORE: [[THEN0]]:
82 ; STORE: br label %[[AFTER0]]
83 ; STORE: [[AFTER0]]:
87 ; STORE: [[THEN1]]:
91 ; STORE: br label %[[AFTER1]]
92 ; STORE: [[AFTER1]]:
96 ; STORE: [[THEN2]]:
101 ; STORE: [[AFTER2]]:
105 ; STORE: [[THEN3]]:
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepIICHVX.td173 InstrItinData <tc_191381c1, /*SLOT0,STORE,VA*/
190 InstrItinData <tc_20a4bbec, /*SLOT0,STORE*/
266 InstrItinData <tc_3ce09744, /*SLOT0,STORE*/
371 InstrItinData <tc_6942b6e0, /*SLOT0,STORE*/
392 InstrItinData <tc_7177e272, /*SLOT0,STORE*/
520 InstrItinData <tc_ab23f776, /*SLOT0,STORE*/
658 InstrItinData <tc_e99d4c2e, /*SLOT0,STORE*/
754 InstrItinData <tc_20a4bbec, /*SLOT0,STORE*/
830 InstrItinData <tc_3ce09744, /*SLOT0,STORE*/
935 InstrItinData <tc_6942b6e0, /*SLOT0,STORE*/
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dhorizontal.ll604 ; STORE-NEXT: entry:
627 ; STORE: for.end:
719 ; STORE-NEXT: entry:
741 ; STORE: for.end:
808 ; STORE-NEXT: entry:
848 ; STORE-NEXT: entry:
912 ; STORE-NEXT: entry:
968 ; STORE-NEXT: entry:
1008 ; STORE-NEXT: entry:
1072 ; STORE-NEXT: entry:
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dcprestore-noreorder-noat.s14 # RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=NO-STORE
17 # RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=NO-STORE
31 # NO-STORE-NOT: sw $gp, 8($sp)
50 # NO-STORE-NOT: sw $gp,
H A Dcprestore-reorder.s5 # RUN: llvm-objdump -d -r - | FileCheck %s --check-prefix=CHECK-FOR-STORE
35 # CHECK-FOR-STORE: sw $gp, 8($sp)
H A Dcprestore-noreorder.s6 # RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefix=CHECK-FOR-STORE
38 # CHECK-FOR-STORE: sw $gp, 8($sp)
/llvm-project-15.0.7/flang/runtime/
H A Dbuffer.h47 template <typename STORE, std::size_t minBuffer = 65536> class FileFrame {
141 STORE &Store() { return static_cast<STORE &>(*this); } in Store()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMemoryLegalizer.cpp45 STORE = 1u << 1, enumerator
46 LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ STORE)
931 assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE); in enableVolatileAndOrNonTemporal()
1283 assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE); in enableVolatileAndOrNonTemporal()
1585 assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE); in enableVolatileAndOrNonTemporal()
1818 assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE); in enableVolatileAndOrNonTemporal()
1846 if (Op == SIMemOp::STORE) in enableVolatileAndOrNonTemporal()
1881 if ((Op & SIMemOp::STORE) != SIMemOp::NONE) in insertWait()
1893 if ((Op & SIMemOp::STORE) != SIMemOp::NONE) in insertWait()
2085 assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE); in enableVolatileAndOrNonTemporal()
[all …]
H A DAMDGPUISelLowering.cpp175 setOperationAction(ISD::STORE, MVT::f32, Promote); in AMDGPUTargetLowering()
176 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
178 setOperationAction(ISD::STORE, MVT::v2f32, Promote); in AMDGPUTargetLowering()
181 setOperationAction(ISD::STORE, MVT::v3f32, Promote); in AMDGPUTargetLowering()
184 setOperationAction(ISD::STORE, MVT::v4f32, Promote); in AMDGPUTargetLowering()
187 setOperationAction(ISD::STORE, MVT::v5f32, Promote); in AMDGPUTargetLowering()
190 setOperationAction(ISD::STORE, MVT::v6f32, Promote); in AMDGPUTargetLowering()
205 setOperationAction(ISD::STORE, MVT::i64, Promote); in AMDGPUTargetLowering()
211 setOperationAction(ISD::STORE, MVT::f64, Promote); in AMDGPUTargetLowering()
474 ISD::STORE, ISD::FADD, in AMDGPUTargetLowering()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/X86/
H A Dpr48844-br-to-switch-vectorization.ll19 ; CHECK-NEXT: i32 -12, label [[STORE:%.*]]
20 ; CHECK-NEXT: i32 13, label [[STORE]]
/llvm-project-15.0.7/llvm/test/TableGen/
H A Ddag-isel-complexpattern.td23 // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::STORE)
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp315 template <> bool AVRDAGToDAGISel::select<ISD::STORE>(SDNode *N) { in select()
567 case ISD::STORE: in trySelect()
568 return select<ISD::STORE>(N); in trySelect()
/llvm-project-15.0.7/openmp/runtime/tools/lib/
H A DPlatform.pm310 sub STORE { subroutine
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dinline-asm.ll234 ; CHECK: v_and_b32_e32 [[STORE:v[0-9]+]], 1, v1
235 ; CHECK: {{buffer|flat}}_store_byte [[STORE]],
/llvm-project-15.0.7/llvm/include/llvm/Target/GlobalISel/
H A DSelectionDAGCompat.td27 // (ISD::LOAD, ISD::ATOMIC_LOAD, ISD::STORE, ISD::ATOMIC_STORE) but GlobalISel
177 // Broadly speaking G_STORE is equivalent to ISD::STORE but there are some
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZPatterns.td39 // with LOAD, OPERATOR and STORE being the read, modify and write
97 // condition is false. Record that they are equivalent to a LOAD/select/STORE
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPNodes.def90 ADD_VVP_OP(VVP_STORE,STORE) HANDLE_VP_TO_VVP(VP_STORE, VVP_STORE) REGISTER_PACKED(VVP_STORE)
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelDAGToDAG.cpp297 case ISD::STORE: in Select()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h967 STORE, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp236 case ISD::STORE: { in matchLSNode()
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dinsn.s75 .insn s STORE, 0, a0, 4(a1)
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dzve32-types.ll9 ; NOTE: The load and store are widened by using VP_LOAD/STORE. The add/fadd are
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl/
H A Dtsan_rtl_access.cpp325 STORE : { in CheckRaces()
378 goto STORE; in CheckRaces()

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