Lines Matching refs:STORE

3 …ore -S < %s -mtriple=x86_64-apple-macosx -mcpu=corei7-avx | FileCheck %s --check-prefixes=ALL,STORE
603 ; STORE-LABEL: @store_red_double(
604 ; STORE-NEXT:  entry:
605 ; STORE-NEXT:    [[CMP17:%.*]] = icmp sgt i32 [[N:%.*]], 0
606 ; STORE-NEXT:    br i1 [[CMP17]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]]
607 ; STORE:       for.body.lr.ph:
608 ; STORE-NEXT:    [[TMP0:%.*]] = bitcast double* [[B:%.*]] to <2 x double>*
609 ; STORE-NEXT:    [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]], align 8
610 ; STORE-NEXT:    [[TMP2:%.*]] = sext i32 [[N]] to i64
611 ; STORE-NEXT:    br label [[FOR_BODY:%.*]]
612 ; STORE:       for.body:
613 ; STORE-NEXT:    [[I_018:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
614 ; STORE-NEXT:    [[MUL:%.*]] = shl nsw i64 [[I_018]], 2
615 ; STORE-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[A:%.*]], i64 [[MUL]]
616 ; STORE-NEXT:    [[TMP3:%.*]] = bitcast double* [[ARRAYIDX2]] to <2 x double>*
617 ; STORE-NEXT:    [[TMP4:%.*]] = load <2 x double>, <2 x double>* [[TMP3]], align 8
618 ; STORE-NEXT:    [[TMP5:%.*]] = fmul fast <2 x double> [[TMP1]], [[TMP4]]
619 ; STORE-NEXT:    [[TMP6:%.*]] = extractelement <2 x double> [[TMP5]], i32 0
620 ; STORE-NEXT:    [[TMP7:%.*]] = extractelement <2 x double> [[TMP5]], i32 1
621 ; STORE-NEXT:    [[ADD8:%.*]] = fadd fast double [[TMP6]], [[TMP7]]
622 ; STORE-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds double, double* [[C:%.*]], i64 [[I_018]]
623 ; STORE-NEXT:    store double [[ADD8]], double* [[ARRAYIDX9]], align 8
624 ; STORE-NEXT:    [[INC]] = add nsw i64 [[I_018]], 1
625 ; STORE-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP2]]
626 ; STORE-NEXT:    br i1 [[EXITCOND]], label [[FOR_END]], label [[FOR_BODY]]
627 ; STORE:       for.end:
628 ; STORE-NEXT:    ret void
718 ; STORE-LABEL: @store_red(
719 ; STORE-NEXT:  entry:
720 ; STORE-NEXT:    [[CMP37:%.*]] = icmp sgt i32 [[N:%.*]], 0
721 ; STORE-NEXT:    br i1 [[CMP37]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]]
722 ; STORE:       for.body.lr.ph:
723 ; STORE-NEXT:    [[TMP0:%.*]] = sext i32 [[N]] to i64
724 ; STORE-NEXT:    br label [[FOR_BODY:%.*]]
725 ; STORE:       for.body:
726 ; STORE-NEXT:    [[I_039:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
727 ; STORE-NEXT:    [[C_ADDR_038:%.*]] = phi float* [ [[C:%.*]], [[FOR_BODY_LR_PH]] ], [ [[INCDEC_PTR:…
728 ; STORE-NEXT:    [[MUL:%.*]] = shl nsw i64 [[I_039]], 2
729 ; STORE-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[MUL]]
730 ; STORE-NEXT:    [[TMP1:%.*]] = bitcast float* [[B:%.*]] to <4 x float>*
731 ; STORE-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
732 ; STORE-NEXT:    [[TMP3:%.*]] = bitcast float* [[ARRAYIDX2]] to <4 x float>*
733 ; STORE-NEXT:    [[TMP4:%.*]] = load <4 x float>, <4 x float>* [[TMP3]], align 4
734 ; STORE-NEXT:    [[TMP5:%.*]] = fmul fast <4 x float> [[TMP2]], [[TMP4]]
735 ; STORE-NEXT:    [[TMP6:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00,…
736 ; STORE-NEXT:    store float [[TMP6]], float* [[C_ADDR_038]], align 4
737 ; STORE-NEXT:    [[INCDEC_PTR]] = getelementptr inbounds float, float* [[C_ADDR_038]], i64 1
738 ; STORE-NEXT:    [[INC]] = add nsw i64 [[I_039]], 1
739 ; STORE-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP0]]
740 ; STORE-NEXT:    br i1 [[EXITCOND]], label [[FOR_END]], label [[FOR_BODY]]
741 ; STORE:       for.end:
742 ; STORE-NEXT:    ret i32 0
807 ; STORE-LABEL: @float_red_example4(
808 ; STORE-NEXT:  entry:
809 ; STORE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* bitcast ([32 x float]* @arr_float to…
810 ; STORE-NEXT:    [[TMP1:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00,…
811 ; STORE-NEXT:    store float [[TMP1]], float* [[RES:%.*]], align 16
812 ; STORE-NEXT:    ret void
847 ; STORE-LABEL: @float_red_example8(
848 ; STORE-NEXT:  entry:
849 ; STORE-NEXT:    [[TMP0:%.*]] = load <8 x float>, <8 x float>* bitcast ([32 x float]* @arr_float to…
850 ; STORE-NEXT:    [[TMP1:%.*]] = call fast float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00,…
851 ; STORE-NEXT:    store float [[TMP1]], float* [[RES:%.*]], align 16
852 ; STORE-NEXT:    ret void
911 ; STORE-LABEL: @float_red_example16(
912 ; STORE-NEXT:  entry:
913 ; STORE-NEXT:    [[TMP0:%.*]] = load <16 x float>, <16 x float>* bitcast ([32 x float]* @arr_float …
914 ; STORE-NEXT:    [[TMP1:%.*]] = call fast float @llvm.vector.reduce.fadd.v16f32(float -0.000000e+00…
915 ; STORE-NEXT:    store float [[TMP1]], float* [[RES:%.*]], align 16
916 ; STORE-NEXT:    ret void
967 ; STORE-LABEL: @i32_red_example4(
968 ; STORE-NEXT:  entry:
969 ; STORE-NEXT:    [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([32 x i32]* @arr_i32 to <4 x i3…
970 ; STORE-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP0]])
971 ; STORE-NEXT:    store i32 [[TMP1]], i32* [[RES:%.*]], align 16
972 ; STORE-NEXT:    ret void
1007 ; STORE-LABEL: @i32_red_example8(
1008 ; STORE-NEXT:  entry:
1009 ; STORE-NEXT:    [[TMP0:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([32 x i32]* @arr_i32 to <8 x i3…
1010 ; STORE-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP0]])
1011 ; STORE-NEXT:    store i32 [[TMP1]], i32* [[RES:%.*]], align 16
1012 ; STORE-NEXT:    ret void
1071 ; STORE-LABEL: @i32_red_example16(
1072 ; STORE-NEXT:  entry:
1073 ; STORE-NEXT:    [[TMP0:%.*]] = load <16 x i32>, <16 x i32>* bitcast ([32 x i32]* @arr_i32 to <16 x…
1074 ; STORE-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP0]])
1075 ; STORE-NEXT:    store i32 [[TMP1]], i32* [[RES:%.*]], align 16
1076 ; STORE-NEXT:    ret void
1183 ; STORE-LABEL: @i32_red_example32(
1184 ; STORE-NEXT:  entry:
1185 ; STORE-NEXT:    [[TMP0:%.*]] = load <32 x i32>, <32 x i32>* bitcast ([32 x i32]* @arr_i32 to <32 x…
1186 ; STORE-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> [[TMP0]])
1187 ; STORE-NEXT:    store i32 [[TMP1]], i32* [[RES:%.*]], align 16
1188 ; STORE-NEXT:    ret void
1481 ; STORE-LABEL: @nsw_propagation_v4i32(
1482 ; STORE-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([32 x i32]* @arr_i32 to <4 x i3…
1483 ; STORE-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]])
1484 ; STORE-NEXT:    [[OP_RDX:%.*]] = add i32 [[TMP2]], [[START:%.*]]
1485 ; STORE-NEXT:    store i32 [[OP_RDX]], i32* [[RES:%.*]], align 16
1486 ; STORE-NEXT:    ret void