| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUAsmPrinter.cpp | 234 if (STM.isAmdHsaOS()) in emitFunctionBodyStart()
451 if (STM.hasGFX90AInsts()) in getAmdhsaKernelDescriptor()
478 if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) { in runOnMachineFunction()
488 if (STM.isAmdPalOS()) { in runOnMachineFunction()
498 if (STM.dumpCode()) { in runOnMachineFunction()
567 if (STM.hasGFX90AInsts()) in runOnMachineFunction()
707 STM.getMaxWaveScratchSize() / STM.getWavefrontSize(); in getSIProgramInfo()
925 S_00B84C_TRAP_HANDLER(STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled()) | in getSIProgramInfo()
1030 if (STM.hasMAIInsts()) { in EmitPALMetadata()
1053 if (STM.isWave32()) in EmitPALMetadata()
[all …]
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| H A D | R600AsmPrinter.cpp | 47 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>(); in EmitProgramInfoR600() local
48 const R600RegisterInfo *RI = STM.getRegisterInfo(); in EmitProgramInfoR600()
71 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) { in EmitProgramInfoR600()
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| H A D | SILoadStoreOptimizer.cpp | 194 const GCNSubtarget *STM = nullptr; member in __anonb64536af0111::SILoadStoreOptimizer
664 EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4); in setMI()
1036 if (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired)) in checkAndPrepareMerge()
1066 offsetsCanBeCombined(CI, *STM, Paired, true); in checkAndPrepareMerge()
1071 if (STM->ldsRequiresM0Init()) in read2Opcode()
1077 if (STM->ldsRequiresM0Init()) in read2ST64Opcode()
1166 if (STM->ldsRequiresM0Init()) in write2Opcode()
1173 if (STM->ldsRequiresM0Init()) in write2ST64Opcode()
2354 STM = &MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
2355 if (!STM->loadStoreOptEnabled()) in runOnMachineFunction()
[all …]
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| H A D | AMDGPUHSAMetadataStreamer.cpp | 193 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getHSACodeProps() local
202 HSACodeProps.mKernargSegmentSize = STM.getKernArgSegmentSize(F, in getHSACodeProps()
209 HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); in getHSACodeProps()
214 HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled(); in getHSACodeProps()
865 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getHSAKernelProps() local
873 STM.getKernArgSegmentSize(F, MaxKernArgAlign)); in getHSAKernelProps()
885 Kern.getDocument()->getNode(STM.getWavefrontSize()); in getHSAKernelProps()
890 if (STM.hasMAIInsts()) { in getHSAKernelProps()
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| H A D | SIMemoryLegalizer.cpp | 1127 const GCNSubtarget &STM = MBB.getParent()->getSubtarget<GCNSubtarget>(); in insertAcquire() local
1129 const unsigned InvalidateL1 = STM.isAmdPalOS() || STM.isMesa3DOS() in insertAcquire()
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| /llvm-project-15.0.7/clang/lib/Tooling/Syntax/ |
| H A D | ComputeReplacements.cpp | 22 const syntax::TokenBufferTokenManager &STM, in enumerateTokenSpans() argument
25 Enumerator(const syntax::TokenBufferTokenManager &STM, in enumerateTokenSpans()
27 : STM(STM), SpanBegin(nullptr), SpanEnd(nullptr), SpanIsOriginal(false), in enumerateTokenSpans()
47 if (SpanEnd == STM.getToken(L->getTokenKey()) && in enumerateTokenSpans()
57 SpanBegin = STM.getToken(L->getTokenKey()); in enumerateTokenSpans()
62 const syntax::TokenBufferTokenManager &STM; in enumerateTokenSpans() member
69 return Enumerator(STM, Callback).run(Root); in enumerateTokenSpans()
72 syntax::FileRange rangeOfExpanded(const syntax::TokenBufferTokenManager &STM, in rangeOfExpanded() argument
74 const auto &Buffer = STM.tokenBuffer(); in rangeOfExpanded()
75 const auto &SM = STM.sourceManager(); in rangeOfExpanded()
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| H A D | BuildTree.cpp | 668 std::string str(const syntax::TokenBufferTokenManager &STM) const { in str()
674 : STM.tokenBuffer().expandedTokens().end() - It->first; in str()
678 It->first->text(STM.sourceManager()), CoveredTokens)); in str()
679 R += It->second->dump(STM); in str()
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| /llvm-project-15.0.7/clang/unittests/Tooling/Syntax/ |
| H A D | TreeTestBase.cpp | 39 const TokenBufferTokenManager &STM) { in tokens() argument
42 return llvm::makeArrayRef(STM.getToken(L->getTokenKey()), 1); in tokens()
44 return llvm::makeArrayRef(STM.getToken(T->findFirstLeaf()->getTokenKey()), in tokens()
45 STM.getToken(T->findLastLeaf()->getTokenKey()) + 1); in tokens()
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| /llvm-project-15.0.7/llvm/test/CodeGen/Thumb/ |
| H A D | stm-scavenging.ll | 4 ; Use STM to save the three registers
22 ; Don't use STM: there is no available register to store
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| /llvm-project-15.0.7/polly/lib/External/isl/imath/tests/ |
| H A D | isprime.tc | 31 # http://csrc.nist.gov/groups/STM/cavp/documents/dss/186-2rsatestvectors.zip
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | cortex-a57-misched-stm.ll | 6 ; We need second, post-ra scheduling to have STM instruction combined from single-stores
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| H A D | cortex-a57-misched-stm-wrback.ll | 6 ; We need second, post-ra scheduling to have STM instruction combined from single-stores
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| H A D | load-store-flags.ll | 26 ; past it to form the STM.
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM7.td | 240 // time for STM cannot be overridden because it is a variadic source operand.
245 (instregex "(t|t2)STM(DB|IA)$")>;
249 (instregex "(t|t2)STM(DB|IA)_UPD$", "tPUSH")>;
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| H A D | ARMScheduleM4.td | 62 def : M4UnitL1I<(instregex "(t|t2)STM")>;
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| H A D | ARMScheduleR52.td | 506 (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
508 (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
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| H A D | ARMScheduleSwift.td | 535 (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
537 (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | invalid-thumbv7.txt | 134 # SP and PC are not allowed in the register list on STM instructions in Thumb2.
360 # 32-bit Thumb STM instructions cannot have a writeback register which appears
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| H A D | thumb1.txt | 386 # STM
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| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | DataLayout.cpp | 682 StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap); in getStructLayout() local
683 StructLayout *&SL = (*STM)[Ty]; in getStructLayout()
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| /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/ |
| H A D | frame-05.ll | 10 ; itself would allow STM and LM to be used instead of STMG and LMG.
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| /llvm-project-15.0.7/libunwind/src/ |
| H A D | UnwindRegistersSave.S | 815 @ . the pc (r15) cannot be in the list in an STM instruction
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| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | diagnostics.s | 313 @ Out of order STM registers
566 @ CHECK-ERRORS: error: system STM cannot have writeback register
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| H A D | basic-thumb-instructions.s | 518 @ STM
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| H A D | thumb-diagnostics.s | 148 @ Invalid writeback and register lists for STM
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