194   const GCNSubtarget *STM = nullptr;  member in __anonb64536af0111::SILoadStoreOptimizer
664     EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4);  in setMI()
976 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM,  in widthsFit()  argument
982     return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));  in widthsFit()
1036     if (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired))  in checkAndPrepareMerge()
1066     offsetsCanBeCombined(CI, *STM, Paired, true);  in checkAndPrepareMerge()
1071   if (STM->ldsRequiresM0Init())  in read2Opcode()
1077   if (STM->ldsRequiresM0Init())  in read2ST64Opcode()
1166   if (STM->ldsRequiresM0Init())  in write2Opcode()
1173   if (STM->ldsRequiresM0Init())  in write2ST64Opcode()
1419       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferLoadPair()
1491       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferStorePair()
2050     static_cast<const SITargetLowering *>(STM->getTargetLowering());  in promoteConstantOffsetToImm()
2354   STM = &MF.getSubtarget<GCNSubtarget>();  in runOnMachineFunction()
2355   if (!STM->loadStoreOptEnabled())  in runOnMachineFunction()
2358   TII = STM->getInstrInfo();  in runOnMachineFunction()