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Searched refs:SSR (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp818 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0; in updatePhiNodes() local
822 SR = RO.getReg(), SSR = RO.getSubReg(); in updatePhiNodes()
833 TR = SR, TSR = SSR; in updatePhiNodes()
835 FR = SR, FSR = SSR; in updatePhiNodes()
H A DHexagonRegisterInfo.td295 def SSR : Rs<6, "ssr", ["s6"]>, DwarfRegNum<[150]>;
377 def S7_6 : Rss<6, "s7:6", [SSR, CCR], ["ccr:ssr"]>, DwarfRegNum<[150]>;
599 SSR, CCR, HTID, BADVA, IMASK,
/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Core/
H A DMemRegion.cpp160 const auto *SSR = dyn_cast<StackSpaceRegion>(getMemorySpace()); in getStackFrame() local
161 return SSR ? SSR->getStackFrame() : nullptr; in getStackFrame()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp780 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaChecking.cpp11416 SourceRange SSR = SizeOfArg->getSourceRange(); in CheckMemaccessArguments() local
11424 SSR = SourceRange(SM.getSpellingLoc(SSR.getBegin()), in CheckMemaccessArguments()
11425 SM.getSpellingLoc(SSR.getEnd())); in CheckMemaccessArguments()
11434 << SSR); in CheckMemaccessArguments()
11438 << SSR); in CheckMemaccessArguments()