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Searched refs:SRsrc (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.h165 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
168 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
173 bool SelectMUBUFScratchOffset(SDNode *Parent, SDValue Addr, SDValue &SRsrc,
176 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
H A DAMDGPUISelDAGToDAG.cpp1334 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, in SelectMUBUFAddr64() argument
1354 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
1450 SDValue &SRsrc, in SelectMUBUFScratchOffset() argument
1461 SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); in SelectMUBUFScratchOffset()
1485 SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); in SelectMUBUFScratchOffset()
1491 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, in SelectMUBUFOffset() argument
1511 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
H A DSILoadStoreOptimizer.cpp94 bool SRsrc = false; member
558 Result.SRsrc = true; in getRegs()
573 Result.SRsrc = true; in getRegs()
584 Result.SRsrc = true; in getRegs()
703 if (Regs.SRsrc) in setMI()
H A DSIInstrInfo.cpp5548 Register SRsrc = MRI.createVirtualRegister(SRsrcRC); in emitLoadSRsrcFromVGPRLoop() local
5551 auto Merge = BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc); in emitLoadSRsrcFromVGPRLoop()
5559 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop()
5855 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc); in legalizeOperands() local
5856 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) in legalizeOperands()
5857 CreatedBB = loadSRsrcFromVGPR(*this, MI, *SRsrc, MDT); in legalizeOperands()