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Searched refs:SRegs (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/test/TableGen/
H A DConcatenatedSubregs.td48 def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>;
67 [(decimate (shl SRegs, 1), 2),
68 (decimate (shl SRegs, 2), 2)]>;
72 (shl SRegs, 0),
73 (shl SRegs, 1),
74 (shl SRegs, 2),
75 (shl SRegs, 3),
76 (shl SRegs, 4)
82 // CHECK-LABEL: RegisterClass SRegs:
H A DGlobalISelEmitterRegSequence.td21 def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 1)>;
28 def SOP : RegisterOperand<SRegs>;
31 def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
H A DRegisterInfoEmitter-regcost.td22 def SRegs : RegisterClass<"MyTarget", [i32], 32, (sequence "S%u", 0, 3)>;
H A DRegisterInfoEmitter-regcost-list.td20 def SRegs : RegisterClass<"MyTarget", [i32], 32, (sequence "S%u", 0, 3)>;
H A DGlobalISelEmitterSubreg.td24 def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 3)>;
33 def SOP : RegisterOperand<SRegs>;
36 def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
37 def SUBSOME_INSN2 : I<(outs SRegs:$dst), (ins SOP:$src), []>;
H A DRegisterInfoEmitter-tsflags.td26 def SRegs : MyClass<32, [i32], (add S)> {
H A DGlobalISelEmitterCustomPredicate.td43 def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 1)>;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp1631 SRegs[*SR] = true; in assignCalleeSavedSpillSlots()
1643 SRegs[*SR] = false; in assignCalleeSavedSpillSlots()
1655 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { in assignCalleeSavedSpillSlots()
1673 SRegs |= TmpSup; in assignCalleeSavedSpillSlots()
1679 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { in assignCalleeSavedSpillSlots()
1682 if (!SRegs[*SR]) in assignCalleeSavedSpillSlots()
1684 SRegs[R] = false; in assignCalleeSavedSpillSlots()
1701 if (!SRegs[S->Reg]) in assignCalleeSavedSpillSlots()
1713 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { in assignCalleeSavedSpillSlots()
1723 SRegs[R] = false; in assignCalleeSavedSpillSlots()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp5291 SmallVector<unsigned, 8> SRegs; in readlaneVGPRToSGPR() local
5297 SRegs.push_back(SGPR); in readlaneVGPRToSGPR()
5304 MIB.addReg(SRegs[i]); in readlaneVGPRToSGPR()