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Searched refs:SReg (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterScavenging.cpp562 if (!isRegUsed(SReg)) { in scavengeRegister()
564 return SReg; in scavengeRegister()
580 << printReg(SReg, TRI) << "\n"); in scavengeRegister()
582 return SReg; in scavengeRegister()
675 MRI.replaceRegWith(VReg, SReg); in scavengeVReg()
677 return SReg; in scavengeVReg()
713 Register SReg = scavengeVReg(MRI, RS, Reg, true); in scavengeFrameVirtualRegsInBlock() local
714 N->addRegisterKilled(SReg, &TRI, false); in scavengeFrameVirtualRegsInBlock()
715 RS.setRegUsed(SReg); in scavengeFrameVirtualRegsInBlock()
739 Register SReg = scavengeVReg(MRI, RS, Reg, false); in scavengeFrameVirtualRegsInBlock() local
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H A DLivePhysRegs.cpp269 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) { in addLiveIns() local
270 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) { in addLiveIns()
H A DPrologEpilogInserter.cpp1246 for (MCPhysReg SReg : TRI.sub_and_superregs_inclusive(Reg)) in insertZeroCallUsedRegs() local
1247 RegsToZero.reset(SReg); in insertZeroCallUsedRegs()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp100 unsigned getDPRLaneFromSPR(unsigned SReg);
115 unsigned getPrefSPRLane(unsigned SReg);
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
154 if (!Register::isVirtualRegister(SReg)) in getPrefSPRLane()
155 return getDPRLaneFromSPR(SReg); in getPrefSPRLane()
157 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
159 MachineOperand *MO = MI->findRegisterDefOperand(SReg); in getPrefSPRLane()
165 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
168 if (Register::isVirtualRegister(SReg)) { in getPrefSPRLane()
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H A DARMBaseInstrInfo.cpp5054 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane() argument
5055 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5062 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DVirtRegMap.h153 void setIsSplitFromReg(Register virtReg, Register SReg) { in setIsSplitFromReg() argument
154 Virt2SplitMap[virtReg.id()] = SReg; in setIsSplitFromReg()
155 if (hasShape(SReg)) { in setIsSplitFromReg()
156 Virt2ShapeMap[virtReg.id()] = getShape(SReg); in setIsSplitFromReg()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp128 Register SReg; in optimizeVccBranch() local
130 SReg = Op2.getReg(); in optimizeVccBranch()
135 if (M->definesRegister(SReg, TRI)) in optimizeVccBranch()
137 if (M->modifiesRegister(SReg, TRI)) in optimizeVccBranch()
139 ReadsSreg |= M->readsRegister(SReg, TRI); in optimizeVccBranch()
148 if (A->getOpcode() == And && SReg == CondReg && !ModifiesExec && in optimizeVccBranch()
190 if (SReg == ExecReg) { in optimizeVccBranch()
H A DSIShrinkInstructions.cpp910 Register SReg = Src2->getReg(); in runOnMachineFunction() local
911 if (SReg.isVirtual()) { in runOnMachineFunction()
912 MRI->setRegAllocationHint(SReg, 0, VCCReg); in runOnMachineFunction()
915 if (SReg != VCCReg) in runOnMachineFunction()
H A DSIInstrInfo.cpp1137 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
1138 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
1145 .addReg(SReg); in insertVectorSelect()
1160 .addReg(SReg); in insertVectorSelect()
1174 .addReg(SReg); in insertVectorSelect()
1181 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
1188 .addReg(SReg); in insertVectorSelect()
1195 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
1202 .addReg(SReg); in insertVectorSelect()
1220 .addReg(SReg); in insertVectorSelect()
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H A DSIRegisterInfo.td1020 defm SSrc : RegImmOperand<"SReg", "SSrc">;
1032 defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ;
H A DSIInstructions.td1299 // FIXME: Why do only some of these type combinations for SReg and
/llvm-project-15.0.7/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DMemRegion.h1018 ParamVarRegion(const Expr *OE, unsigned Idx, const MemRegion *SReg) in ParamVarRegion() argument
1019 : VarRegion(SReg, ParamVarRegionKind), OriginExpr(OE), Index(Idx) { in ParamVarRegion()
1020 assert(!cast<StackSpaceRegion>(SReg)->getStackFrame()->inTopFrame()); in ParamVarRegion()
1025 unsigned Idx, const MemRegion *SReg);
1254 const SubRegion *SReg) in CXXBaseObjectRegion() argument
1255 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) { in CXXBaseObjectRegion()
1260 bool IsVirtual, const MemRegion *SReg);
1292 CXXDerivedObjectRegion(const CXXRecordDecl *DerivedD, const SubRegion *SReg) in CXXDerivedObjectRegion() argument
1293 : TypedValueRegion(SReg, CXXDerivedObjectRegionKind), DerivedD(DerivedD) { in CXXDerivedObjectRegion()
1298 assert(SReg->getSymbolicBase() && in CXXDerivedObjectRegion()
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/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Core/
H A DMemRegion.cpp310 unsigned Idx, const MemRegion *SReg) { in ProfileRegion() argument
314 ID.AddPointer(SReg); in ProfileRegion()
398 const MemRegion *SReg) { in ProfileRegion() argument
401 ID.AddPointer(SReg); in ProfileRegion()
410 const MemRegion *SReg) { in ProfileRegion() argument
412 ID.AddPointer(SReg); in ProfileRegion()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp1608 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex() local
1613 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) in eliminateFrameIndex()
1618 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) in eliminateFrameIndex()
1623 TII.materializeImmPostRA(MBB, II, dl, SReg, Offset); in eliminateFrameIndex()
1647 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); in eliminateFrameIndex()
1656 .addReg(SReg, RegState::Kill) in eliminateFrameIndex()
H A DPPCISelLowering.cpp11703 Register SReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
11704 BuildMI(BB, dl, TII->get(PPC::AND), SReg) in EmitPartwordAtomicBinary()
11707 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary()
11712 .addReg(SReg) in EmitPartwordAtomicBinary()
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4861 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
4869 if (DReg == SReg) { in expandRotation()
4909 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4924 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
4950 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
4986 unsigned SReg = Inst.getOperand(1).getReg(); in expandDRotation() local
4994 if (TmpReg == SReg) { in expandDRotation()
5034 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
5049 unsigned SReg = Inst.getOperand(1).getReg(); in expandDRotationImm() local
5086 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandDRotationImm()
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