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Searched refs:SRA (Results 1 – 25 of 119) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h37 SRA = 0x37, enumerator
96 case SRA: in lanaiAluCodeToString()
114 .Case("sha", SRA) in stringToLanaiAluCode()
138 case ISD::SRA: in isdToLanaiAluCode()
139 return AluCode::SRA; in isdToLanaiAluCode()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp371 { ISD::SRA, MVT::v2i64, 1 }, in getArithmeticInstrCost()
372 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
373 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
739 { ISD::SRA, MVT::v16i8, 2 }, in getArithmeticInstrCost()
742 { ISD::SRA, MVT::v8i16, 2 }, in getArithmeticInstrCost()
745 { ISD::SRA, MVT::v4i32, 2 }, in getArithmeticInstrCost()
748 { ISD::SRA, MVT::v2i64, 2 }, in getArithmeticInstrCost()
752 { ISD::SRA, MVT::v32i8, 4+2 }, in getArithmeticInstrCost()
755 { ISD::SRA, MVT::v16i16, 4+2 }, in getArithmeticInstrCost()
758 { ISD::SRA, MVT::v8i32, 4+2 }, in getArithmeticInstrCost()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dshift-09.ll50 ; Check that we use SRAK over SRA where useful.
61 ; Check that we use SRA over SRAK where possible.
H A Dshift-03.ll6 ; Check the low end of the SRA range.
16 ; Check the high end of the defined SRA range.
/llvm-project-15.0.7/llvm/test/MC/Mips/mips1/
H A Dvalid.s132 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
135 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
138 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
141 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
/llvm-project-15.0.7/llvm/test/Transforms/GlobalOpt/
H A Dglobalsra-multigep.ll7 ; We cannot SRA here due to the second gep meaning the access to g_data may be to either element
H A Dglobalsra-recursive.ll4 ; Make sure we don't recursively SRA if there are aggregate load/stores with
H A Dglobalsra-opaque-ptr.ll4 ; Global SRA should not be performed here (or at least not naively), as
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dvalid.s173 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
176 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
179 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
182 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp167 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence() local
169 return SRA; in addIPMSequence()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp60 setOperationAction(ISD::SRA, MVT::i32, Custom); in LoongArchTargetLowering()
124 case ISD::SRA: in LowerOperation()
294 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts()
311 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, GRLenMinus1) : Zero; in lowerShiftRightParts()
330 case ISD::SRA: in getLoongArchWOpcode()
360 case ISD::SRA: in ReplaceNodeResults()
424 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dbitwise.mir270 ; MIPS32: [[SRA:%[0-9]+]]:gpr32 = SRA [[COPY]], 1
271 ; MIPS32: $v0 = COPY [[SRA]]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A Dvalid.s236 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
239 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
242 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
245 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp98 case ISD::SRA: in PromoteIntegerResult()
900 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
1675 case ISD::SRA: in PromoteIntegerOperand()
2510 case ISD::SRA: in ExpandIntegerResult()
2722 case ISD::SRA: in ExpandShiftWithKnownAmountBit()
2828 case ISD::SRA: in ExpandShiftWithUnknownAmountBit()
3293 ISD::SRA, dl, NVT, Hi, in ExpandIntRes_ABS()
3376 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, in ExpandIntRes_FLT_ROUNDS()
4266 ISD::SRA, dl, NVT, Lo, in ExpandIntRes_SIGN_EXTEND()
4443 SDValue SRA = in ExpandIntRes_XMULO() local
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32/
H A Dvalid.s234 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
237 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
240 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
243 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp83 setOperationAction(ISD::SRA, MVT::i8, Custom); in AVRTargetLowering()
86 setOperationAction(ISD::SRA, MVT::i16, Custom); in AVRTargetLowering()
305 case ISD::SRA: in LowerShifts()
315 case ISD::SRA: in LowerShifts()
361 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) { in LowerShifts()
366 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) { in LowerShifts()
373 if (Op.getOpcode() == ISD::SRA) in LowerShifts()
425 case ISD::SRA: in LowerShifts()
451 case ISD::SRA: in LowerShifts()
844 case ISD::SRA: in LowerOperation()
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r5/
H A Dvalid.s283 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
286 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
289 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
292 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s282 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
285 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
288 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
291 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r3/
H A Dvalid.s282 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
285 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
288 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
291 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcombine-sra-load.ll89 ; Fold even if SRA has multiple uses.
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64/
H A Dvalid.s315 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
318 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
321 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
324 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dvalid.s296 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
299 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
302 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
305 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
/llvm-project-15.0.7/llvm/test/MC/Mips/mips5/
H A Dvalid.s297 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
300 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
303 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
306 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPNodes.def102 ADD_BINARY_VVP_OP(VVP_SRA,VP_ASHR,SRA) REGISTER_PACKED(VVP_SRA)

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