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/llvm-project-15.0.7/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp61 SP::G0, SP::G1, SP::G2, SP::G3,
62 SP::G4, SP::G5, SP::G6, SP::G7,
63 SP::O0, SP::O1, SP::O2, SP::O3,
64 SP::O4, SP::O5, SP::O6, SP::O7,
65 SP::L0, SP::L1, SP::L2, SP::L3,
66 SP::L4, SP::L5, SP::L6, SP::L7,
67 SP::I0, SP::I1, SP::I2, SP::I3,
68 SP::I4, SP::I5, SP::I6, SP::I7 };
71 SP::F0, SP::F1, SP::F2, SP::F3,
72 SP::F4, SP::F5, SP::F6, SP::F7,
[all …]
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_trampoline_AArch64.S22 STP X1, X2, [SP, #-16]!
23 STP X3, X4, [SP, #-16]!
24 STP X5, X6, [SP, #-16]!
48 LDP X8, X0, [SP], #16
49 LDP Q6, Q7, [SP], #32
50 LDP Q4, Q5, [SP], #32
51 LDP Q2, Q3, [SP], #32
52 LDP Q0, Q1, [SP], #32
54 LDP X5, X6, [SP], #16
55 LDP X3, X4, [SP], #16
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
69 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
82 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
225 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) in emitEpilogue()
312 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) in verifyLeafProcRegUse()
343 unsigned mapped_reg = reg - SP::I0 + SP::O0; in remapRegsForLeafProc()
362 MBB.addLiveIn(reg - SP::I0_I1 + SP::O0_O1); in remapRegsForLeafProc()
[all …]
H A DSparcRegisterInfo.cpp58 Reserved.set(SP::G1); in getReservedRegs()
70 Reserved.set(SP::O6); in getReservedRegs()
71 Reserved.set(SP::I6); in getReservedRegs()
72 Reserved.set(SP::I7); in getReservedRegs()
73 Reserved.set(SP::G0); in getReservedRegs()
132 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) in replaceFI()
137 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) in replaceFI()
150 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) in replaceFI()
152 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1) in replaceFI()
155 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) in replaceFI()
[all …]
H A DDelaySlotFiller.cpp179 if (Opc == SP::RET || Opc == SP::TLS_CALL) in findDelayInstr()
182 if (Opc == SP::RETL || Opc == SP::TAIL_CALL || Opc == SP::TAIL_CALLri) { in findDelayInstr()
277 Opcode >= SP::LDDArr && Opcode <= SP::LDrr) in delayHasHazard()
283 Opcode >= SP::FDIVD && Opcode <= SP::FSQRTD) in delayHasHazard()
387 if (reg < SP::I0 || reg > SP::I7) in combineRestoreADD()
399 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
415 if (reg < SP::I0 || reg > SP::I7) in combineRestoreOR()
438 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
453 if (reg < SP::I0 || reg > SP::I7) in combineRestoreSETHIi()
472 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
[all …]
H A DSparcInstrInfo.cpp35 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(), in SparcInstrInfo()
45 if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri || in isLoadFromStackSlot()
46 MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri || in isLoadFromStackSlot()
64 if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri || in isStoreToStackSlot()
65 MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri || in isStoreToStackSlot()
146 return Opc == SP::FBCOND || Opc == SP::BCOND; in isCondBranchOpcode()
150 return Opc == SP::BINDrr || Opc == SP::BINDri; in isIndirectBranchOpcode()
314 const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; in copyPhysReg()
317 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd, in copyPhysReg()
322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
[all …]
H A DSparcAsmPrinter.cpp109 CallInst.setOpcode(SP::CALL); in EmitCall()
119 SETHIInst.setOpcode(SP::SETHIi); in EmitSETHI()
176 assert(MO.getReg() != SP::O7 && in LowerGETPCXAndEmitMCInsts()
261 case SP::GETPCX: in emitInstruction()
279 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 }; in emitFunctionBodyStart()
285 if (reg == SP::G6 || reg == SP::G7) in emitFunctionBodyStart()
301 if (MI->getOpcode() == SP::CALL) in printOperand()
304 else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi) in printOperand()
315 else if (MI->getOpcode() == SP::TLS_CALL) in printOperand()
326 else if (MI->getOpcode() == SP::TLS_LDrr) in printOperand()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp29 using namespace SP;
60 case SP::JMPLrr: in printSparcAliasInstr()
61 case SP::JMPLri: { in printSparcAliasInstr()
84 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: in printSparcAliasInstr()
85 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { in printSparcAliasInstr()
182 case SP::BPFCC: in printCCOperand()
186 case SP::MOVFCCrr: case SP::V9MOVFCCrr: in printCCOperand()
187 case SP::MOVFCCri: case SP::V9MOVFCCri: in printCCOperand()
188 case SP::FMOVS_FCC: case SP::V9FMOVS_FCC: in printCCOperand()
189 case SP::FMOVD_FCC: case SP::V9FMOVD_FCC: in printCCOperand()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Darguments-varargs.ll36 ; O32-DAG: sw $7, 20([[SP]])
37 ; O32-DAG: sw $6, 16([[SP]])
38 ; O32-DAG: sw $5, 12([[SP]])
40 ; NEW-DAG: sd $11, 56([[SP]])
41 ; NEW-DAG: sd $10, 48([[SP]])
42 ; NEW-DAG: sd $9, 40([[SP]])
43 ; NEW-DAG: sd $8, 32([[SP]])
44 ; NEW-DAG: sd $7, 24([[SP]])
45 ; NEW-DAG: sd $6, 16([[SP]])
46 ; NEW-DAG: sd $5, 8([[SP]])
[all …]
/llvm-project-15.0.7/llvm/unittests/ExecutionEngine/Orc/
H A DSymbolStringPoolTest.cpp19 SymbolStringPool SP; in TEST() local
20 auto P1 = SP.intern("hello"); in TEST()
24 auto P2 = SP.intern(S); in TEST()
38 SymbolStringPool SP; in TEST() local
39 auto Foo = SP.intern("foo"); in TEST()
44 SymbolStringPool SP; in TEST() local
47 SP.clearDeadEntries(); in TEST()
50 SP.clearDeadEntries(); in TEST()
55 SymbolStringPool SP; in TEST() local
56 auto A1 = SP.intern("a"); in TEST()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll8 define void @foo(double %vfp0, ; --> D0, NSAA=SP
9 double %vfp1, ; --> D1, NSAA=SP
10 double %vfp2, ; --> D2, NSAA=SP
11 double %vfp3, ; --> D3, NSAA=SP
12 double %vfp4, ; --> D4, NSAA=SP
13 double %vfp5, ; --> D5, NSAA=SP
14 double %vfp6, ; --> D6, NSAA=SP
15 double %vfp7, ; --> D7, NSAA=SP
16 double %vfp8, ; --> SP, NSAA=SP+8 (!)
18 %st_t* byval(%st_t) %p1, ; --> SP+8, 4 words NSAA=SP+24
[all …]
H A D2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll10 define void @foo(double %vfp0, ; --> D0, NSAA=SP
12 double %vfp2, ; --> D2, NSAA=SP
13 double %vfp3, ; --> D3, NSAA=SP
14 double %vfp4, ; --> D4, NSAA=SP
15 double %vfp5, ; --> D5, NSAA=SP
16 double %vfp6, ; --> D6, NSAA=SP
17 double %vfp7, ; --> D7, NSAA=SP
18 double %vfp8, ; --> SP, NSAA=SP+8 (!)
20 %st_t* byval(%st_t) %p1, ; --> R1, R2, NSAA=SP+8
21 i32 %p2, ; --> R3, NSAA=SP+8
[all …]
H A Dfpconv.ll9 ;CHECK-VFP-SP-LABEL: f1:
10 ;CHECK-VFP-SP: bl __aeabi_d2f
21 ;CHECK-VFP-SP-LABEL: f2:
33 ;CHECK-VFP-SP-LABEL: f3:
34 ;CHECK-VFP-SP: vcvt.s32.f32
45 ;CHECK-VFP-SP-LABEL: f4:
57 ;CHECK-VFP-SP-LABEL: f5:
69 ;CHECK-VFP-SP-LABEL: f6:
81 ;CHECK-VFP-SP-LABEL: f7:
93 ;CHECK-VFP-SP-LABEL: f8:
[all …]
H A Dfloat-helpers.s55 ; CHECK-HARDFP-SP-LABEL: fadd:
78 ; CHECK-HARDFP-SP-LABEL: fdiv:
101 ; CHECK-HARDFP-SP-LABEL: fmul:
124 ; CHECK-HARDFP-SP-LABEL: fsub:
151 ; CHECK-HARDFP-SP-LABEL: fcmpeq:
182 ; CHECK-HARDFP-SP-LABEL: fcmplt:
779 ; CHECK-HARDFP-SP-LABEL: d2lz:
832 ; CHECK-HARDFP-SP-LABEL: f2iz:
1057 ; CHECK-HARDFP-SP-LABEL: l2d:
1110 ; CHECK-HARDFP-SP-LABEL: i2f:
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dframe-27.mir20 # CHECK: alloc FI(1) at SP[-4255]
21 # CHECK-NEXT: alloc FI(0) at SP[-4271]
22 # CHECK-NEXT: alloc FI(2) at SP[-4280]
23 # CHECK-NEXT: alloc FI(3) at SP[-4288]
43 # CHECK: alloc FI(0) at SP[-176]
44 # CHECK-NEXT: alloc FI(1) at SP[-4271]
45 # CHECK-NEXT: alloc FI(2) at SP[-4280]
46 # CHECK-NEXT: alloc FI(3) at SP[-4288]
66 # CHECK: alloc FI(1) at SP[-8350]
67 # CHECK-NEXT: alloc FI(0) at SP[-12445]
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darmv8.4a-ldst-error.s7 STLURB SP, [X1, #1]
8 ldapurb SP, [x12, #1]
13 STLURB W3, [SP, #-257]
17 LDAPURB W6, [SP, #256]
29 STLURH W12, [SP, #-257]
33 LDAPURH W15, [SP, #256]
41 LDAPURSH X5, [SP, #256]
45 STLUR W21, [SP, #-257]
53 LDAPURSW X8, [SP, #-257]
57 STLUR X11, [SP, #256]
H A Darmv8.4a-ldst.s15 STLURB W3, [SP, #-3]
26 LDAPURB W6, [SP, #-2]
59 STLURH W12, [SP, #1]
69 LDAPURH W15, [SP, #2]
89 LDAPURSH X5, [SP, #4]
99 STLUR W21, [SP, #5]
119 LDAPURSW X8, [SP, #7]
129 STLUR X11, [SP, #8]
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Dbyval.ll22 ; Subtract 16 from SP (SP is 16-byte aligned)
26 ; Ensure SP is stored back before the call
29 ; Copy the SmallStruct argument to the stack (SP+12, original SP-4)
31 ; CHECK-NEXT: i32.store 12($[[SP]]), $pop[[L0]]
39 ; CHECK-NEXT: i32.add $push[[L8:.+]]=, $[[SP]], $pop[[L6]]
53 ; Copy the SmallStruct argument to the stack (SP+8, original SP-8)
55 ; CHECK-NEXT: i32.store 8($[[SP]]), $pop[[L0]]{{$}}
67 ; Subtract 16 from SP (SP is 16-byte aligned)
72 ; Copy the AlignedStruct argument to the stack (SP+0, original SP-16)
75 ; CHECK-NEXT: i64.store 0($[[SP]]), $pop[[L4]]
[all …]
H A Dmulti-return.ll25 ; CHECK: i32.add $push1=, $[[SP]], $pop0
42 ; CHECK: i32.add $push3=, $[[SP]], $pop2
57 ; CHECK: i32.add $push1=, $[[SP]], $pop0
87 ; CHECK: i64.load $push2=, 16($[[SP]])
108 ; CHECK: i32.add $push3=, $[[SP]], $pop2
111 ; CHECK: i64.load $push4=, 56($[[SP]])
133 ; CHECK: i32.add $push3=, $[[SP]], $pop2
136 ; CHECK: i64.load $push4=, 32($[[SP]])
162 ; CHECK: i32.add $push3=, $[[SP]], $pop2
165 ; CHECK: i32.add $push5=, $[[SP]], $pop4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dbuildpairf64-extractelementf64-implicit-sp.ll4 ; RUN: FileCheck %s -check-prefix=FPXX-IMPLICIT-SP
9 ; RUN: FileCheck %s -check-prefix=FP64-IMPLICIT-SP
14 ; RUN: FileCheck %s -check-prefix=NO-IMPLICIT-SP
18 ; FPXX-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
19 ; FPXX-IMPLICIT-SP: ExtractElementF64 killed %{{[0-9]+}}, 1, implicit $sp
20 ; FP64-IMPLICIT-SP: BuildPairF64_64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
21 ; FP64-IMPLICIT-SP: ExtractElementF64_64 killed %{{[0-9]+}}, 1, implicit $sp
22 ; NO-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}
23 ; NO-IMPLICIT-SP-NOT: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
24 ; NO-IMPLICIT-SP: ExtractElementF64 killed %{{[0-9]+}}, 1
[all …]
/llvm-project-15.0.7/lldb/tools/debugserver/source/
H A DJSON.cpp122 JSONValue::SP value(iter->second); in Write()
140 return JSONValue::SP(); in GetObject()
217 JSONValue::SP JSONArray::GetObject(Index i) { in GetObject()
220 return JSONValue::SP(); in GetObject()
505 return JSONValue::SP(); in ParseJSONObject()
508 JSONValue::SP JSONParser::ParseJSONArray() { in ParseJSONArray()
535 return JSONValue::SP(); in ParseJSONArray()
578 return JSONValue::SP(new JSONTrue()); in ParseJSONValue()
581 return JSONValue::SP(new JSONFalse()); in ParseJSONValue()
584 return JSONValue::SP(new JSONNull()); in ParseJSONValue()
[all …]
H A DJSON.h29 typedef std::shared_ptr<JSONValue> SP; typedef
54 typedef std::shared_ptr<JSONString> SP; typedef
72 typedef std::shared_ptr<JSONNumber> SP; typedef
142 typedef std::shared_ptr<JSONTrue> SP; typedef
160 typedef std::shared_ptr<JSONFalse> SP; typedef
178 typedef std::shared_ptr<JSONNull> SP; typedef
240 typedef std::shared_ptr<JSONArray> SP; typedef
257 JSONValue::SP GetObject(Index i);
292 JSONValue::SP ParseJSONValue();
297 JSONValue::SP ParseJSONObject();
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DJMCInstrumenter.cpp65 std::string getFlagName(DISubprogram &SP, bool UseX86FastCall) { in getFlagName() argument
73 SP.getDirectory().contains("\\") || in getFlagName()
74 SP.getFilename().contains("\\") in getFlagName()
82 SmallString<256> FilePath(SP.getDirectory()); in getFlagName()
83 sys::path::append(FilePath, PathStyle, SP.getFilename()); in getFlagName()
104 void attachDebugInfo(GlobalVariable &GV, DISubprogram &SP) { in attachDebugInfo() argument
106 DICompileUnit *CU = SP.getUnit(); in attachDebugInfo()
161 auto *SP = F.getSubprogram(); in runOnModule() local
162 if (!SP) in runOnModule()
165 Constant *&Flag = SavedFlags[SP]; in runOnModule()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dlocal-stack-frame.ll9 ; PTX32: cvta.local.u32 %SP, %SPL;
11 ; PTX32: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
13 ; PTX64: cvta.local.u64 %SP, %SPL;
15 ; PTX64: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
23 ; PTX32: cvta.local.u32 %SP, %SPL;
28 ; PTX64: cvta.local.u64 %SP, %SPL;
45 ; PTX32-NOT: cvta.local.u32 %SP, %SPL;
50 ; PTX64-NOT: cvta.local.u64 %SP, %SPL;
62 ; PTX32: cvta.local.u32 %SP, %SPL;
63 ; PTX32: add.u32 {{%r[0-9]+}}, %SP, 0;
[all …]
/llvm-project-15.0.7/lld/test/wasm/
H A Dmutable-global-exports.s43 # CHECK-SP: - Type: EXPORT
44 # CHECK-SP-NEXT: Exports:
45 # CHECK-SP-NEXT: - Name: memory
46 # CHECK-SP-NEXT: Kind: MEMORY
47 # CHECK-SP-NEXT: Index: 0
49 # CHECK-SP-NEXT: Kind: GLOBAL
50 # CHECK-SP-NEXT: Index: 0
51 # CHECK-SP-NEXT: - Name: _start
52 # CHECK-SP-NEXT: Kind: FUNCTION
53 # CHECK-SP-NEXT: Index: 0
[all …]

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