35     : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),  in SparcInstrInfo()
45   if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri ||  in isLoadFromStackSlot()
46       MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri ||  in isLoadFromStackSlot()
47       MI.getOpcode() == SP::LDQFri) {  in isLoadFromStackSlot()
64   if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri ||  in isStoreToStackSlot()
65       MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri ||  in isStoreToStackSlot()
66       MI.getOpcode() == SP::STQFri) {  in isStoreToStackSlot()
143 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; }  in isUncondBranchOpcode()
146   return Opc == SP::FBCOND || Opc == SP::BCOND;  in isCondBranchOpcode()
150   return Opc == SP::BINDrr || Opc == SP::BINDri;  in isIndirectBranchOpcode()
255     BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);  in insertBranch()
263     BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);  in insertBranch()
265     BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);  in insertBranch()
269   BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);  in insertBranch()
285     if (I->getOpcode() != SP::BA  in removeBranch()
286         && I->getOpcode() != SP::BCOND  in removeBranch()
287         && I->getOpcode() != SP::FBCOND)  in removeBranch()
314   const unsigned DW_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd };  in copyPhysReg()
315   const unsigned DFP_FP_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd };  in copyPhysReg()
316   const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };  in copyPhysReg()
317   const unsigned QFP_FP_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd,  in copyPhysReg()
318                                           SP::sub_odd64_then_sub_even,  in copyPhysReg()
319                                           SP::sub_odd64_then_sub_odd };  in copyPhysReg()
321   if (SP::IntRegsRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
322     BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)  in copyPhysReg()
324   else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {  in copyPhysReg()
327     movOpc     = SP::ORrr;  in copyPhysReg()
329   } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
330     BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)  in copyPhysReg()
332   else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {  in copyPhysReg()
334       BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)  in copyPhysReg()
340       movOpc     = SP::FMOVS;  in copyPhysReg()
342   } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {  in copyPhysReg()
345         BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)  in copyPhysReg()
351         movOpc     = SP::FMOVD;  in copyPhysReg()
357       movOpc     = SP::FMOVS;  in copyPhysReg()
359   } else if (SP::ASRRegsRegClass.contains(DestReg) &&  in copyPhysReg()
360              SP::IntRegsRegClass.contains(SrcReg)) {  in copyPhysReg()
361     BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)  in copyPhysReg()
362         .addReg(SP::G0)  in copyPhysReg()
364   } else if (SP::IntRegsRegClass.contains(DestReg) &&  in copyPhysReg()
365              SP::ASRRegsRegClass.contains(SrcReg)) {  in copyPhysReg()
366     BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)  in copyPhysReg()
384       MIB.addReg(SP::G0);  in copyPhysReg()
409   if (RC == &SP::I64RegsRegClass)  in storeRegToStackSlot()
410     BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)  in storeRegToStackSlot()
412   else if (RC == &SP::IntRegsRegClass)  in storeRegToStackSlot()
413     BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)  in storeRegToStackSlot()
415   else if (RC == &SP::IntPairRegClass)  in storeRegToStackSlot()
416     BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0)  in storeRegToStackSlot()
418   else if (RC == &SP::FPRegsRegClass)  in storeRegToStackSlot()
419     BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)  in storeRegToStackSlot()
421   else if (SP::DFPRegsRegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
422     BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)  in storeRegToStackSlot()
424   else if (SP::QFPRegsRegClass.hasSubClassEq(RC))  in storeRegToStackSlot()
427     BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)  in storeRegToStackSlot()
447   if (RC == &SP::I64RegsRegClass)  in loadRegFromStackSlot()
448     BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)  in loadRegFromStackSlot()
450   else if (RC == &SP::IntRegsRegClass)  in loadRegFromStackSlot()
451     BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)  in loadRegFromStackSlot()
453   else if (RC == &SP::IntPairRegClass)  in loadRegFromStackSlot()
454     BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0)  in loadRegFromStackSlot()
456   else if (RC == &SP::FPRegsRegClass)  in loadRegFromStackSlot()
457     BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)  in loadRegFromStackSlot()
459   else if (SP::DFPRegsRegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
460     BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)  in loadRegFromStackSlot()
462   else if (SP::QFPRegsRegClass.hasSubClassEq(RC))  in loadRegFromStackSlot()
465     BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)  in loadRegFromStackSlot()
483     Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;  in getGlobalBaseReg()
488   BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);  in getGlobalBaseReg()
500     MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));  in expandPostRAPseudo()
502         .addReg(SP::G7)  in expandPostRAPseudo()