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Searched refs:SLT (Results 1 – 25 of 32) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp535 if (SLT == MVT::i64) in getArithmeticInstrCost()
538 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
548 if (SLT == MVT::i64) { in getArithmeticInstrCost()
553 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
559 if (SLT == MVT::i64) { in getArithmeticInstrCost()
596 if (SLT == MVT::f64) in getArithmeticInstrCost()
602 if (SLT == MVT::f32 || SLT == MVT::f16) in getArithmeticInstrCost()
609 if (SLT == MVT::f64) { in getArithmeticInstrCost()
639 if (SLT == MVT::f32 || SLT == MVT::f16) { in getArithmeticInstrCost()
655 return TLI->isFNegFree(SLT) ? 0 : NElts; in getArithmeticInstrCost()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dicmp.mir85 ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
86 ; MIPS32: $v0 = COPY [[SLT]]
110 ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
111 ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
136 ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
137 ; MIPS32: $v0 = COPY [[SLT]]
161 ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
162 ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp311 unsigned LL, SC, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOpSubword() local
319 SLT = Mips::SLT_MM; in expandAtomicBinOpSubword()
331 SLT = Mips::SLT; in expandAtomicBinOpSubword()
457 unsigned SLTScratch4 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOpSubword()
586 unsigned LL, SC, ZERO, BEQ, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOp() local
593 SLT = Mips::SLT_MM; in expandAtomicBinOp()
608 SLT = Mips::SLT; in expandAtomicBinOp()
623 SLT = Mips::SLT64; in expandAtomicBinOp()
743 unsigned SLTScratch2 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOp()
H A DMipsCondMov.td199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
244 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
251 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
H A DMipsInstructionSelector.cpp787 Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS); in select()
790 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); in select()
794 Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS); in select()
797 Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS); in select()
H A DMipsFastISel.cpp678 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
681 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
685 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
691 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
H A DMipsInstrInfo.td2066 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>,
2732 (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
2735 (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
3281 defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>,
3335 defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
3336 defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1;
3337 defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
H A DMipsScheduleP5600.td225 SEB, SEH, SLT, SLTu, SLL, SRA, SRL, XORi,
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/loop-idiom/
H A Dmemmove-rt-check.ll11 ; CHECK: [[SLT:%[0-9]+]] = icmp sle i32 [[LEN]], [[SUB]]
12 ; CHECK: [[CND:%[0-9]+]] = or i1 [[ULT]], [[SLT]]
/llvm-project-15.0.7/polly/test/ScopInfo/
H A Dcfg_consequences.ll15 ; SLT: *A = 0;
247 br label %SLT
249 SLT: ; preds = %if.end.3
258 M_SLT: ; preds = %S_SLT, %SLT
/llvm-project-15.0.7/llvm/test/CodeGen/SPIRV/instructions/
H A Dptrcmp.ll8 ; CHECK-DAG: OpName [[SLT:%.*]] "test_slt"
41 ; CHECK: [[SLT]] = OpFunction
H A Dicmp.ll8 ; CHECK-DAG: OpName [[SLT:%.*]] "test_slt"
51 ; CHECK: [[SLT]] = OpFunction
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dinstalias-imm-expanding.s566 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
574 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
592 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
600 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
606 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
613 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td649 def SLT : ALU_rr<0b0000000, 0b010, "slt">,
870 def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
871 def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
875 def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>;
1255 def : PatGprGpr<setlt, SLT>;
1273 def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
1274 def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
1275 def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
1285 def : Pat<(ineg (setge GPR:$rs1, GPR:$rs2)), (ADDI (SLT GPR:$rs1, GPR:$rs2), -1)>;
1286 def : Pat<(ineg (setle GPR:$rs1, GPR:$rs2)), (ADDI (SLT GPR:$rs2, GPR:$rs1), -1)>;
H A DRISCVSExtWRemoval.cpp233 case RISCV::SLT: in isSignExtendingOpW()
H A DRISCVInstrInfoZb.td978 (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
980 (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-cmp-44.ll49 ; ...and again with SLT.
142 ; ...and again with SLT.
278 ; ...and SLT.
374 ; ...and the SLT case.
H A Dbranch-07.ll52 ; Test SLT.
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td306 def SLT : ALU_3R<0b00000000000100100, "slt">;
691 def : PatGprGpr<setlt, SLT>;
721 def : Pat<(setgt GPR:$rj, GPR:$rk), (SLT GPR:$rk, GPR:$rj)>;
722 def : Pat<(setge GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rj, GPR:$rk), 1)>;
723 def : Pat<(setle GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rk, GPR:$rj), 1)>;
/llvm-project-15.0.7/llvm/test/Transforms/CorrelatedValuePropagation/
H A Dadd.ll311 ; because the loop exit condition is SLT, we can supplement the iv add
H A Dsub.ll474 ; because the loop exit condition is SLT, we can supplement the iv sub
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/
H A D3r.mir59 $r4 = SLT $r5, $r4
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4143 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, in expandCondBranches()
4548 OpCode = Mips::SLT; in expandSge()
4583 OpRegCode = Mips::SLT; in expandSgeImm()
4640 OpCode = Mips::SLT; in expandSgtImm()
4685 OpCode = Mips::SLT; in expandSle()
4720 OpRegCode = Mips::SLT; in expandSleImm()
4798 FinalOpcode = Mips::SLT; in expandAliasImmediate()
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dcanonicalize-clamp-like-pattern-between-zero-and-positive-threshold.ll17 ; Also, SLT predicate can also be SGE; or SGT iff C2 != INT_MAX (+invert res.)
H A Dcanonicalize-clamp-like-pattern-between-negative-and-positive-thresholds.ll17 ; Also, SLT predicate can also be SGE; or SGT iff C2 != INT_MAX (+invert res.)

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