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Searched refs:SLLW (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSExtWRemoval.cpp107 case RISCV::SLLW: in isAllUsesReadW()
204 case RISCV::SLLW: in isSignExtendingOpW()
H A DRISCVISelLowering.h63 SLLW, enumerator
H A DRISCVInstrInfo.td72 def riscv_sllw : SDNode<"RISCVISD::SLLW", SDT_RISCVIntBinOpW>;
741 def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">,
1580 // PatFrag to allow ADDW/SUBW/MULW/SLLW to be selected from i64 add/sub/mul/shl
1613 def : PatGprGpr<shiftopw<riscv_sllw>, SLLW>;
H A DRISCVISelDAGToDAG.cpp2155 case RISCV::SLLW: in hasAllNBitUsers()
H A DRISCVISelLowering.cpp6788 return RISCVISD::SLLW; in getRISCVWOpcode()
8157 if (N0.getOpcode() == RISCVISD::SLLW && in performXORCombine()
8888 case RISCVISD::SLLW: in PerformDAGCombine()
9665 case RISCVISD::SLLW: in ComputeNumSignBitsForTargetNode()
11620 NODE_NAME_CASE(SLLW) in getTargetNodeName()