Home
last modified time | relevance | path

Searched refs:SIMD (Results 1 – 25 of 96) sorted by relevance

1234

/llvm-project-15.0.7/flang/docs/
H A DOpenMP-4.5-grammar.md61 2.8.1 simd -> SIMD [simd-clause[ [,] simd-clause]...]
71 2.8.1 end-simd -> END SIMD
81 2.8.3 do-simd -> DO SIMD [do-simd-clause[ [,] do-simd-clause]...]
85 2.8.3 end-do-simd -> END DO SIMD [nowait-clause]
123 2.9.3 end-taskloop-simd -> END TASKLOOP SIMD
200 2.10.9 end-distribute-simd -> END DISTRIBUTE SIMD
237 2.11.4 end-parallel-do-simd -> END PARALLEL DO SIMD
256 2.11.7 end-target-parallel-do-simd -> END TARGET PARALLEL DO SIMD
262 2.11.8 end-target-simd -> END TARGET SIMD
281 2.11.11 end-teams-distribute-simd -> END TEAMS DISTRIBUTE SIMD
[all …]
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/portability/
H A Dsimd-intrinsics.rst6 Finds SIMD intrinsics calls and suggests ``std::experimental::simd`` (`P0214`_)
22 Many architectures provide SIMD operations (e.g. x86 SSE/AVX, Power AltiVec/VSX,
23 ARM NEON). It is common that SIMD code implementing the same algorithm, is
27 The C++ standard proposal `P0214`_ and its extensions cover many common SIMD
29 operations, the SIMD code can be simplified and pieces for different targets can
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArch.td51 // Loongson SIMD eXtension (LSX)
54 "'LSX' (Loongson SIMD Extension)", [FeatureBasicD]>;
58 "'LSX' (Loongson SIMD Extension)">;
60 // Loongson Advanced SIMD eXtension (LASX)
63 "'LASX' (Loongson Advanced SIMD Extension)",
68 "'LASX' (Loongson Advanced SIMD Extension)">;
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dresource-optimization-remarks.ll9 ; STDERR-NEXT: remark: foo.cl:27:0: Occupancy [waves/SIMD]: 5
65 ; REMARK-NEXT: - String: ' Occupancy [waves/SIMD]: '
111 ; STDERR-NEXT: remark: foo.cl:42:0: Occupancy [waves/SIMD]: 0
127 ; STDERR-NEXT: remark: foo.cl:8:0: Occupancy [waves/SIMD]: 10
140 ; STDERR-NEXT: remark: foo.cl:52:0: Occupancy [waves/SIMD]: 0
/llvm-project-15.0.7/polly/test/ScheduleOptimizer/
H A Dprevectorization.ll64 ; CHECK: // SIMD
74 ; CHECK: // SIMD
84 ; VEC16: // SIMD
94 ; VEC16: // SIMD
H A Dvivid-vbi-gen-vivid_vbi_gen_sliced-before-llvmreduced.ll42 ; CHECK: mark: "SIMD"
44 ; CHECK: mark: "SIMD"
H A Dprevectorization-without-tiling.ll59 ; CHECK: // SIMD
66 ; CHECK: // SIMD
H A Dfocaltech_test_detail_threshold-7bc17e.ll86 ; CHECK: mark: "SIMD"
93 ; CHECK: mark: "SIMD"
H A Dfull_partial_tile_separation.ll13 ; CHECK-NEXT: // SIMD
21 ; CHECK-NEXT: // SIMD
H A Drectangular-tiling.ll59 ; TWO-PLUS-REGISTER-PLUS-VECTORIZATION: // SIMD
62 ; TWO-PLUS-REGISTER-PLUS-VECTORIZATION: // SIMD
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleSwift.td556 // 4.2.28 Advanced SIMD, Integer, 2 cycle
567 // 4.2.29 Advanced SIMD, Integer, 4 cycle
584 // 4.2.32 Advanced SIMD, Vector Table Lookup
597 // 4.2.33 Advanced SIMD, Transpose
602 // 4.2.34 Advanced SIMD and VFP, Floating Point
612 // 4.2.35 Advanced SIMD and VFP, Multiply
622 // 4.2.36 Advanced SIMD and VFP, Convert
625 // 4.2.37 Advanced SIMD and VFP, Move
652 // 4.2.38 Advanced SIMD and VFP, Move FPSCR
679 // 4.2.41 Advanced SIMD and VFP, Load Multiple
[all …]
/llvm-project-15.0.7/pstl/
H A DREADME.md15 * Support for OpenMP* 4.0 SIMD constructs
23 * The following algorithms do not allow efficient SIMD execution: `includes`, `inplace_merge`, `mer…
/llvm-project-15.0.7/clang/test/Frontend/
H A Damdgcn-machine-analysis-remarks.cl9 // expected-remark@+4 {{ Occupancy [waves/SIMD]: 10}}
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Dsimd-illegal-signext.ll5 ; implemented. Since SIMD is enabled, sign_ext_inreg is custom lowered
H A DPR40267.ll5 ; that SIMD is not enabled for this test. Check only that llc does not
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Arithmetic/IR/
H A DArithmeticOps.td193 // SIMD vector element-wise addition, e.g. for Intel SSE.
243 // SIMD vector element-wise division.
272 // SIMD vector element-wise division.
370 // SIMD vector element-wise division remainder.
399 // SIMD vector element-wise division remainder.
427 // SIMD vector element-wise bitwise integer and.
456 // SIMD vector element-wise bitwise integer or.
485 // SIMD vector element-wise bitwise integer xor.
582 // SIMD vector element-wise negation value.
610 // SIMD vector addition, e.g. for Intel SSE.
[all …]
/llvm-project-15.0.7/clang/docs/
H A DOpenMPSupport.rst131 | loop | clause: if for SIMD directives | :go…
165 | SIMD | atomic and simd constructs inside SIMD code | :go…
167 | SIMD | SIMD nontemporal | :go…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/WebAssembly/
H A Dwasm.txt41 # Check LEB128 encoding of SIMD instructions
/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/AArch64/
H A Dvararg.ll28 ; one for floating-point/SIMD ones, and one for thre remaining arguments.
63 ; point and SIMD are saved from 64 to 192, and the remaining from 192.
/llvm-project-15.0.7/mlir/include/mlir/Dialect/ArmNeon/
H A DArmNeon.td79 source SIMD&FP registers, places the results in a vector, and writes the
80 vector to the destination SIMD&FP register.
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dadd_vp.ll34 ; Mixing regular SIMD with vp intrinsics (vp add match root).
47 ; Mixing regular SIMD with vp intrinsics (vp inside pattern, regular instruction root).
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsWebAssembly.td142 // SIMD intrinsics
222 // Relaxed SIMD intrinsics (experimental)
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DBuiltinsWebAssembly.def68 // SIMD builtins
164 // Relaxed SIMD builtins (experimental)
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DP10InstrResources.td1475 // 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands
1481 // 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands
1494 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands
1520 // 10 Cycles SIMD Matrix Multiply Engine operations, 4 input operands
1527 // 10 Cycles SIMD Matrix Multiply Engine operations, 5 input operands
1546 // 10 Cycles SIMD Matrix Multiply Engine operations, 6 input operands
1565 // 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands
1572 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix…
/llvm-project-15.0.7/llvm/lib/Support/BLAKE3/
H A DCMakeLists.txt20 # "For each of the x86 SIMD instruction sets, four versions are available:

1234