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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsi-spill-sgpr-stack.ll9 ; SGPR: buffer_load_dword [[VHI:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:4
10 ; SGPR-NEXT: s_waitcnt vmcnt(0)
11 ; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 0
12 ; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 1
13 ; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 2
14 ; SGPR-NEXT: v_readlane_b32 s[[HI:[0-9]+]], [[VHI]], 3
15 ; SGPR-NEXT: buffer_load_dword [[VHI]], off, s[96:99], 0
16 ; SGPR-NEXT: s_waitcnt vmcnt(0)
17 ; SGPR-NEXT: s_mov_b64 exec, s[4:5]
18 ; SGPR-NEXT: s_nop 1
[all …]
H A Duse-sgpr-multiple-times.ll11 ; GCN: s_load_dword [[SGPR:s[0-9]+]],
12 ; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
21 ; GCN: s_load_dword [[SGPR:s[0-9]+]],
22 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
100 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
101 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0
110 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
111 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], 2.0, [[SGPR]]
121 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
122 ; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]]
[all …]
H A Dillegal-sgpr-to-vgpr-copy.ll4 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_i32 void (): illegal SGPR to VGP…
13 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v2i32 void (): illegal SGPR to V…
21 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v4i32 void (): illegal SGPR to V…
29 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v8i32 void (): illegal SGPR to V…
37 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v16i32 void (): illegal SGPR to …
45 ; ERR: error: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_i32 void (): illegal SGPR to VGP…
54 ; ERR: error: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_v2i32 void (): illegal SGPR to V…
H A Dsgpr-regalloc-flags.ll20 ; DEFAULT-NEXT: SI lower SGPR spill instructions
29 ; O0-NEXT: SI lower SGPR spill instructions
44 ; BASIC-DEFAULT-NEXT: SI lower SGPR spill instructions
60 ; DEFAULT-BASIC-NEXT: SI lower SGPR spill instructions
78 ; BASIC-BASIC-NEXT: SI lower SGPR spill instructions
89 ; Something with some CSR SGPR spills
H A Dlo16-hi16-illegal-copy.mir6 # Note: GFX8 did not allow SDWA SGPR sources. Therefor no HI16 subregs can be used there.
10 # ERR: error: <unknown>:0:0: in function lo_to_lo_illegal_vgpr_to_sgpr void (): illegal SGPR to VGP…
35 # ERR: error: <unknown>:0:0: in function lo_to_lo_illegal_agpr_to_sgpr void (): illegal SGPR to VGP…
H A Dllvm.amdgcn.readfirstlane.ll46 ; CHECK-NEXT: s_mov_b32 [[SGPR:s[0-9]+]]
48 ; CHECK-NOT: [[SGPR]]
50 ; CHECK: v_mov_b32_e32 [[VCOPY:v[0-9]+]], [[SGPR]]
H A Dspill-alloc-sgpr-init-bug.ll3 ; On Tonga and Iceland, limited SGPR availability means care must be taken to
17 ; mark 128-bit SGPR registers as used so they are unavailable for the
H A Dadd_i64.ll20 ; Check that the SGPR add operand is correctly moved to a VGPR.
31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
32 ; SGPR as other operand.
H A Dllvm.amdgcn.readlane.ll67 ; CHECK-NEXT: s_mov_b32 [[SGPR:s[0-9]+]]
69 ; CHECK-NOT: [[SGPR]]
71 ; CHECK: v_mov_b32_e32 [[VCOPY:v[0-9]+]], [[SGPR]]
H A Dsgpr-spill-to-vmem-scc-clobber-unhandled.mir8 # CHECK: error: unhandled SGPR spill to memory
9 # CHECK: error: unhandled SGPR spill to memory
H A Dfold-fi-operand-shrink.mir56 # First operand is FI is in an SGPR, other operand is a VGPR
81 # First operand is an SGPR, other operand FI is in a VGPR
106 # First operand is FI is in an SGPR, other operand is a VGPR
131 # First operand is a VGPR, other operand FI is in an SGPR
H A Dspill-offset-calculation.ll4 ; Test that the VGPR spiller correctly switches to SGPR offsets when the
34 ; fit in the instruction, and has to live in the SGPR offset.
55 ; FIXME: If we fail to scavenge an SGPR in a kernel we don't have a stack
62 ; fit in the instruction, and has to live in the SGPR offset.
113 ; fit in the instruction, and has to live in the SGPR offset.
196 ; in the SGPR offset.
251 ; fit in the instruction, and has to live in the SGPR offset.
311 ; in the SGPR offset.
H A Dmir-print-dead-csr-fi.mir4 # CSR SGPR frame indexes are inserted, but deleted.
H A Dlo16-lo16-physreg-copy-sgpr.mir4 # Note: GFX8 did not allow SDWA SGPR sources. Therefor no HI16 subregs can be used there.
H A Dsgpr-copy-duplicate-operand.ll4 ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
H A Dmove-addr64-rsrc-dead-subreg-writes.ll6 ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32
H A Dsgpr-spill-dead-frame-in-dbg-value.mir3 # After handling the SGPR spill to VGPR in SILowerSGPRSpills pass, replace the dead frame index in …
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td976 [llvm_v4i32_ty, // rsrc(SGPR)
991 [llvm_v4i32_ty, // rsrc(SGPR)
1000 llvm_v4i32_ty, // rsrc(SGPR)
1020 [llvm_v4i32_ty, // rsrc(SGPR)
1034 [llvm_v4i32_ty, // rsrc(SGPR)
1050 llvm_v4i32_ty, // rsrc(SGPR)
1065 llvm_v4i32_ty, // rsrc(SGPR)
1177 llvm_v4i32_ty, // rsrc(SGPR)
1212 llvm_v4i32_ty, // rsrc(SGPR)
1242 llvm_v4i32_ty, // rsrc(SGPR)
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td303 // SGPR registers
305 defm SGPR#Index :
366 // SGPR 32-bit registers
376 // SGPR 64-bit registers
382 // SGPR 128-bit registers
394 // SGPR 256-bit registers
397 // SGPR 512-bit registers
400 // SGPR 1024-bit registers
1017 // SSrc_* Operands with an SGPR or a 32-bit immediate
1029 // SCSrc_* Operands with an SGPR or a inline constant
[all …]
H A DAMDGPUCallingConv.td156 (sequence "SGPR%u", 30, 105)
160 (add (sequence "SGPR%u", 4, 31), (sequence "SGPR%u", 64, 105))
234 (add (sequence "SGPR%u", 0, 105), VCC_LO, VCC_HI)
H A DAMDGPURegisterBanks.td9 def SGPRRegBank : RegisterBank<"SGPR",
/llvm-project-15.0.7/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
H A Dinline-asm.ll58 ; One output is SGPR, one is VGPR. Infer divergent for the aggregate, but uniform on the SGPR extra…
/llvm-project-15.0.7/llvm/docs/AMDGPU/
H A Dgfx8_hwreg.rst51 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
H A Dgfx7_hwreg.rst51 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dflat-scratch-init.gfx.ll6 ; doesn't add a user SGPR for initializing flat_scratch, mesa does

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