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Searched refs:SETOGE (Results 1 – 25 of 36) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1429 SETOGE, // 0 0 1 1 True if ordered and greater than or equal enumerator
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td357 defm : BRCond_Bin_F2<SETOGE, "f2FCMPHS", BT32, MVC32>;
374 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),
376 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)),
378 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td337 defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, MVC32>;
354 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),
356 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)),
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp192 case FCmpInst::FCMP_OGE: return ISD::SETOGE; in getFCmpCondCode()
216 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp78 case ISD::SETOGE: in fpCondCode2Fcc()
H A DVEInstrInfo.td2080 def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGE)),
2082 def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOGE)),
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td86 defm GE : ComparisonFP<SETOGE, "ge ", 0x60, 0x66>;
H A DWebAssemblyInstrSIMD.td736 defm GE : SIMDConditionFP<"ge", SETOGE, 70>;
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td157 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
H A DLoongArchFloat64InstrInfo.td161 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
H A DLoongArchISelLowering.cpp68 static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE, in LoongArchTargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp448 case ISD::SETOGE: return "setoge"; in getOperationName()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4056 case ISD::SETOGE: in SelectCC()
4083 case ISD::SETOGE: in SelectCC()
4121 case ISD::SETOGE: in getPredicateForSetCC()
4172 case ISD::SETOGE: in getCRIdxForSetCC()
4196 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break; in getVCmpInst()
4207 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
4227 case ISD::SETOGE: in getVCmpInst()
H A DPPCISelLowering.cpp658 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in PPCTargetLowering()
659 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in PPCTargetLowering()
1199 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand); in PPCTargetLowering()
7961 case ISD::SETOGE: in LowerSELECT_CC()
7999 case ISD::SETOGE: in LowerSELECT_CC()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td328 def COND_OGE : PatFrags<(ops), [(OtherVT SETOGE), (OtherVT SETGE)]>;
H A DSIWholeQuadMode.cpp862 case ISD::SETOGE: in lowerKillF32()
H A DAMDGPUISelLowering.cpp1353 case ISD::SETOGE: in combineFMinMaxLegacy()
1656 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE); in LowerDIVREM24()
2176 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp256 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in MipsSETargetLowering()
261 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in MipsSETargetLowering()
393 setCondCodeAction(ISD::SETOGE, Ty, Expand); in addMSAFloatType()
H A DMipsMSAInstrInfo.td128 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
129 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp857 case ISD::SETOGE: in IntCondCCodeToICC()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp302 setCondCodeAction(ISD::SETOGE, MVT::v64f16, Expand); in initializeHVXLowering()
315 setCondCodeAction(ISD::SETOGE, MVT::v32f32, Expand); in initializeHVXLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td744 def SETOGE : CondCode<"FCMP_OGE">;
1350 (setcc node:$lhs, node:$rhs, SETOGE)>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td1794 defm FCMGE_PPzZZ : sve_fp_3op_p_pd_cc<0b000, "fcmge", SETOGE, SETGE, SETOLE, SETLE>;
1802 defm FCMGE_PPzZ0 : sve_fp_2op_p_pd<0b000, "fcmge", SETOGE, SETGE, SETOLE, SETLE>;
1805 defm FCMLE_PPzZ0 : sve_fp_2op_p_pd<0b011, "fcmle", SETOLE, SETLE, SETOGE, SETGE>;
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp547 case ISD::SETOGE: in getPTXCmpMode()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1583 case ISD::SETOGE: in TranslateM68kCC()

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