| /llvm-project-15.0.7/llvm/docs/Proposals/ |
| H A D | VectorPredication.rst | 41 - VP intrinsics translate to first-class SDNodes
44 SDNodes to pre-existing ones (SSE, NEON)).
46 Result: Backend development based on VP SDNodes.
54 - Incrementally lift DAGCombiner to work on VP SDNodes as well as on regular
73 lower to VP SDNodes (from Stage 2).
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VVPInstrInfo.td | 9 // This file defines the VE Vector Predicated SDNodes (VVP SDNodes). VVP
10 // SDNodes are an intermediate isel layer between the vector SDNodes emitted by
18 // TODO explain how VVP nodes relate to VP SDNodes once VP ISel is uptream.
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| H A D | VEInstrPatternsVec.td | 1 //===-- VEInstrPatternsVec.td - VEC_-type SDNodes and isel for VE Target --===//
9 // This file describes the VEC_* prefixed intermediate SDNodes and their
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| H A D | VVPNodes.def | 9 // This file defines all VVP_* SDNodes and their properties
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| H A D | VVPInstrPatternsVec.td | 9 // This file describes how VVP_* SDNodes are lowered to machine instructions.
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| /llvm-project-15.0.7/llvm/docs/GlobalISel/ |
| H A D | InstructionSelect.rst | 69 Custom SDNodes
72 Custom SDNodes should be mapped to Target Pseudos using ``GINodeEquiv``. This
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| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | mmo-target-flags-folding.ll | 4 ; a LOAD SDNodes with different flags.
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| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | targetLoweringGeneric.ll | 5 ; can't be tested easily by checking the SDNodes that are
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| /llvm-project-15.0.7/llvm/test/DebugInfo/X86/ |
| H A D | pr40427.ll | 11 ;; SDNodes that produce no instructions.
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| H A D | ghost-sdnode-dbgvalues.ll | 21 ; This map was never purged when the SDNodes were deallocated and thus if a new
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenDAGPatterns.h | 1106 std::map<Record*, SDNodeInfo, LessRecordByID> SDNodes; variable
1142 auto F = SDNodes.find(R); in getSDNodeInfo()
1143 assert(F != SDNodes.end() && "Unknown node!"); in getSDNodeInfo()
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| H A D | CodeGenDAGPatterns.cpp | 3236 SDNodes.insert(std::make_pair(R, SDNodeInfo(R, CGH))); in ParseNodeInfo()
3368 assert(!SDNodes.empty() && "No SDNodes parsed?"); in ParseDefaultOperands()
3369 Init *SomeSDNode = DefInit::get(SDNodes.begin()->first); in ParseDefaultOperands()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | Relocation.txt | 32 independent and machine specific SDNodes (for example:
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | README.txt | 486 Some of them may also be lowered to target-independent SDNodes, and perhaps
487 some new SDNodes could be added.
496 the target-independent SDNodes for these operations.
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 362 // SDNodes PatFrags for loads/stores with a glue input.
363 // This is for SDNodes and PatFrag for local loads and stores to
633 // SDNodes PatFrags for a16 loads and stores with 3 components.
675 // SDNodes PatFrags for d16 loads
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| H A D | R600Instructions.td | 365 // R600 SDNodes
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcInstr64Bit.td | 313 // We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrAtomics.td | 258 // the SDNodes are derived from AtomicSDNode rather than LoadSDNode and
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoVVLPatterns.td | 1661 // Miscellaneous RISCVISD SDNodes
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 43 // SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags
362 // Frags for commonly used SDNodes.
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | SourceLevelDebugging.rst | 566 metadata is attached to SDNodes in SelectionDAGs. After instruction selection
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.td | 1404 // Create SDNodes so they can be used in the DAG code, e.g.
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