| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 39 struct S31 { virtual void f(); }; struct
85 S30, S31, S32, S33, S34, S35, S36, S37, S38, S39,
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | microsoft-abi-static-initializers.cpp | 90 static S S31; in MultipleStatics() local
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| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | swim.c | 35 S31(c0);
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| H A D | swim.st | 1 …<= P; S44[i0, i1] : M = 1 and i0 >= 2 and i0 <= P and i1 >= 1 and i1 <= Q; S31[i0] : M = 1 and i0 …
33 - filter: "[M, N, O, P, Q, R] -> { S30[i0, i1]; S28[i0, i1]; S31[i0]; S29[i0, i1] }"
35 …schedule: "[M, N, O, P, Q, R] -> [{ S31[i0] -> [(i0)]; S29[i0, i1] -> [(i0)]; S30[i0, i1] -> [(i0)…
48 - filter: "[M, N, O, P, Q, R] -> { S31[i0] }"
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| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | aix-cc-byval.ll | 801 %struct.S31 = type <{ float, i32, i64, double, i32, i16, i8 }>
803 @gS31 = external global %struct.S31, align 1
807 %call = call double @test_byval_31Byte(%struct.S31* byval(%struct.S31) align 1 @gS31)
881 define double @test_byval_31Byte(%struct.S31* byval(%struct.S31) align 1 %s) {
883 %gep = getelementptr inbounds %struct.S31, %struct.S31* %s, i32 0, i32 3
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 62 case AArch64::S31: in isOdd()
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| H A D | AArch64RegisterInfo.td | 360 def S31 : AArch64Reg<31, "s31", [H31]>, DwarfRegAlias<B31>;
395 def D31 : AArch64Reg<31, "d31", [S31], ["v31", ""]>, DwarfRegAlias<B31>;
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| H A D | AArch64AsmPrinter.cpp | 1137 else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31) in emitFMov0()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 117 def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
136 def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>;
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| H A D | ARMExpandPseudoInsts.cpp | 1152 (Reg >= ARM::S0 && Reg <= ARM::S31)) in determineFPRegsToClear()
1163 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) { in determineFPRegsToClear()
1509 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) in CMSESaveClearFPRegsV81()
1670 (Reg >= ARM::S0 && Reg <= ARM::S31)) in definesOrUsesFPReg()
1709 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) in CMSERestoreFPRegsV81()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 280 {codeview::RegisterId::ARM_FS31, ARM::S31}, in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 169 {codeview::RegisterId::ARM64_S31, AArch64::S31}, in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 125 // CHECK-NEXT: %[[S31:.*]] = vector.constant_mask [2, 2] : vector<2x2xi1>
127 …on"], kind = #vector.kind<add>} %[[S27]], %[[S28]], %[[S29]], %[[S30]], %[[S31]] : vector<2x2xf32>…
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 280 S23, S24, S25, S26, S27, S28, S29, S30, S31
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| H A D | PPCFrameLowering.cpp | 194 {PPC::S31, -8}, in getCalleeSavedSpillSlots()
2071 unsigned MinVR = Subtarget.hasSPE() ? PPC::S31 : PPC::V31; in processFunctionBeforeFrameFinalized()
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| H A D | PPCRegisterInfo.td | 337 S31, S0, S1)>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1500 ARM::S28, ARM::S29, ARM::S30, ARM::S31
|