| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | usvd_e_t.c | 131 S24(8, 4, 1);
135 S24(8, 4, 2);
137 S24(8, 4, 3);
145 S24(8, 5, 1);
149 S24(8, 5, 2);
151 S24(8, 5, 3);
159 S24(8, 6, 1);
163 S24(8, 6, 2);
165 S24(8, 6, 3);
213 S24(9, 4, 2);
[all …]
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| H A D | usvd_e_t.st | 1 … i1, i2] : i0 >= 8 and i1 <= 4 and i2 >= -4 and i2 <= 0 and i1 >= -6 + i0; S24[i0, i1, i2] : i0 >=…
5 …S24[i0, i1, i2] -> [(i0)]; S15[i0, i1, i2] -> [(i0)]; S12[i0, i1, i2] -> [(i0)]; S7[i0, i1, i2] ->…
32 - filter: "{ S24[i0, i1, i2] }"
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| H A D | swim.c | 25 S24();
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| H A D | swim.st | 1 …<= P; S47[i0, i1] : M = 1 and i0 >= 2 and i0 <= P and i1 >= 1 and i1 <= Q; S24[] : M = 1; S16[] : …
29 - filter: "[M, N, O, P, Q, R] -> { S24[] }"
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 123 struct S24 { struct
152 S14*, S15*, S16*, S17*, S18*, S19*, S20*, S21*, S22*, S23*, S24*, S25*, in f() argument
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| H A D | microsoft-abi-static-initializers.cpp | 83 static S S24; in MultipleStatics() local
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| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 32 struct S24 { virtual void f(); }; struct
84 S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
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| /llvm-project-15.0.7/llvm/test/Assembler/ |
| H A D | datalayout-invalid-stack-natural-alignment.ll | 5 target datalayout = "S24"
|
| /llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/ |
| H A D | LegalizerHelperTest.cpp | 90 LLT S24 = LLT::scalar(24); in TEST_F() local
91 auto Src = B.buildTrunc(S24, Copies[0]); in TEST_F()
92 auto Amt = B.buildTrunc(S24, Copies[1]); in TEST_F()
93 auto ROTR = B.buildInstr(TargetOpcode::G_ROTR, {S24}, {Src, Amt}); in TEST_F()
94 auto ROTL = B.buildInstr(TargetOpcode::G_ROTL, {S24}, {Src, Amt}); in TEST_F()
101 Helper.lower(*ROTR, 0, S24)); in TEST_F()
103 Helper.lower(*ROTL, 0, S24)); in TEST_F()
1762 const LLT S24 = LLT::scalar(24); in TEST_F() local
1787 auto Merge0 = B.buildMerge(S24, Merge0Ops); in TEST_F()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 108 case AArch64::S24: in isOdd()
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| H A D | AArch64RegisterInfo.td | 353 def S24 : AArch64Reg<24, "s24", [H24]>, DwarfRegAlias<B24>;
388 def D24 : AArch64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias<B24>;
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 313 def S24 : Rs<24, "s24">, DwarfRegNum<[168]>;
386 def S25_24 : Rss<24, "s25:24", [S24, S25]>, DwarfRegNum<[168]>;
602 EVB, MODECTL, SYSCFG, S20, VID, S22, S24,
|
| /llvm-project-15.0.7/llvm/test/Transforms/MemCpyOpt/ |
| H A D | nonlocal-memcpy-memcpy.ll | 123 ; CHECK-NEXT: [[S24:%.*]] = bitcast %struct.s* [[S]] to i8*
|
| /llvm-project-15.0.7/clang/test/Modules/ |
| H A D | odr_hash.cpp | 3147 struct S24 { struct
3153 struct S24 { struct
3159 S24 s24;
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 114 def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
133 def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 273 {codeview::RegisterId::ARM_FS24, ARM::S24}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 162 {codeview::RegisterId::ARM64_S24, AArch64::S24}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 116 // CHECK-NEXT: %[[S24:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [4, 2], sizes = [2, 2]…
118 …arallel", "parallel", "reduction"], kind = #vector.kind<add>} %[[S23]], %[[S24]], %[[R2S02]], %[[S…
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 280 S23, S24, S25, S26, S27, S28, S29, S30, S31
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| H A D | PPCFrameLowering.cpp | 201 {PPC::S24, -64}, in getCalleeSavedSpillSlots()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 786 Hexagon::S24, Hexagon::S25, Hexagon::S26,
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1499 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
|