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Searched refs:Rsrc (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp5477 MachineOperand &Rsrc) { in emitLoadSRsrcFromVGPRLoop() argument
5495 Register VRsrc = Rsrc.getReg(); in emitLoadSRsrcFromVGPRLoop()
5496 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef()); in emitLoadSRsrcFromVGPRLoop()
5498 unsigned RegSize = TRI->getRegSizeInBits(Rsrc.getReg(), MRI); in emitLoadSRsrcFromVGPRLoop()
5559 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop()
5560 Rsrc.setIsKill(true); in emitLoadSRsrcFromVGPRLoop()
5585 MachineOperand &Rsrc, MachineDominatorTree *MDT, in loadSRsrcFromVGPR() argument
5898 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx); in legalizeOperands() local
5900 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()), in legalizeOperands()
5961 Rsrc->setReg(NewSRsrc); in legalizeOperands()
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H A DAMDGPUISelDAGToDAG.cpp1376 SDValue Addr, SDValue &Rsrc, in SelectMUBUFScratchOffen() argument
1384 Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); in SelectMUBUFScratchOffen()
1504 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | in SelectMUBUFOffset() local
1511 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
H A DSIISelLowering.h75 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
H A DSIISelLowering.cpp6669 SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, in lowerSBuffer() argument
6686 Rsrc, in lowerSBuffer()
6724 Rsrc, // rsrc in lowerSBuffer()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmubuf-legalize-operands.ll8 ; Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.
H A Dmubuf-legalize-operands.mir8 # Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.