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Searched refs:Rs2 (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td395 def : Pat<(LanaiSubbF GPR:$Rs1, GPR:$Rs2),
396 (SUBB_F_R GPR:$Rs1, GPR:$Rs2)>;
470 def : Pat<(srl GPR:$Rs1, GPR:$Rs2),
471 (SRL_R GPR:$Rs1, (SUB_R R0, GPR:$Rs2))>;
472 def : Pat<(sra GPR:$Rs1, GPR:$Rs2),
473 (SRA_R GPR:$Rs1, (SUB_R R0, GPR:$Rs2))>;
487 let Rs2 = src{14-10};
606 let Rs2 = dst{14-10};
690 def JR : InstRR<0b101, (outs), (ins GPR:$Rs2), "bt\t$Rs2",
691 [(brind GPR:$Rs2)]> {
[all …]
H A DLanaiInstrFormats.td112 // opcode Rd Rs1 Rs2 \ operation /
115 // `Rd <- Rs1 op Rs2' iff condition DDDI is true.
129 // determined by the contents of `Rs2' interpreted as a two's complement
132 // condition DDDI is true, Rs2 otherwise. All other `JJJJJ' combinations
152 bits<5> Rs2;
162 let Inst{15 - 11} = Rs2;
225 // opcode Rd Rs1 Rs2 \ operation /
234 // 1. `Rs1 + constant' is replaced with `Rs1 op Rs2', where `op' is
261 bits<5> Rs2;
275 let Inst{15 - 11} = Rs2;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp414 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdRs2() local
416 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); in decodeRVCInstrRdRs2()
424 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdRs1Rs2() local
427 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); in decodeRVCInstrRdRs1Rs2()