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/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dalu64.ll5 define i32 @test00(i64 %Rs, i64 %Rt) #0 {
45 define i32 @test12(i32 %Rs) #0 {
53 define i32 @test13(i32 %Rs) #0 {
85 define i32 @test23(i32 %Rs) #0 {
93 define i32 @test24(i32 %Rs) #0 {
101 define i32 @test25(i32 %Rs) #0 {
133 define i32 @test33(i32 %Rs) #0 {
141 define i32 @test34(i32 %Rs) #0 {
149 define i32 @test35(i32 %Rs) #0 {
437 define i32 @test90(i32 %Rs) #0 {
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H A Dusr-ovf-dep.ll15 define i32 @foo(i32 %Rs, i32 %Rt, i32 %Ru) #0 {
17 %0 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %Rs, i32 %Ru)
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsics.td12 : Pat <(IntID I32:$Rs),
13 (MI I32:$Rs)>;
16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
73 (A2_sxtb IntRegs:$Rs)>;
75 (A2_sxth IntRegs:$Rs)>;
93 (A2_tfr I32:$Rs)>;
95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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H A DHexagonPatterns.td274 def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>;
275 def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>;
493 def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>;
1028 def: Pat<(v2i32 (splat_vector I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>;
1133 def: Pat<(rotl I32:$Rs, u5_0ImmPred:$S), (FShl32i $Rs, $Rs, imm:$S)>;
1134 def: Pat<(rotl I64:$Rs, u6_0ImmPred:$S), (FShl64i $Rs, $Rs, imm:$S)>;
1138 def: Pat<(rotl I32:$Rs, I32:$Rt), (FShl32r $Rs, $Rs, $Rt)>;
1139 def: Pat<(rotl I64:$Rs, I32:$Rt), (FShl64r $Rs, $Rs, $Rt)>;
1167 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (FShr32i $Rs, $Rs, imm:$S)>;
1172 def: Pat<(rotr I32:$Rs, I32:$Rt), (FShr32r $Rs, $Rs, $Rt)>;
[all …]
H A DHexagonRegisterInfo.td90 // Rs - system registers
91 class Rs<bits<7> num, string n,
289 def SGP0 : Rs<0, "sgp0", ["s0"]>, DwarfRegNum<[144]>;
290 def SGP1 : Rs<1, "sgp1", ["s1"]>, DwarfRegNum<[145]>;
291 def STID : Rs<2, "stid", ["s2"]>, DwarfRegNum<[146]>;
292 def ELR : Rs<3, "elr", ["s3"]>, DwarfRegNum<[147]>;
293 def BADVA0 : Rs<4, "badva0", ["s4"]>, DwarfRegNum<[148]>;
294 def BADVA1 : Rs<5, "badva1", ["s5"]>, DwarfRegNum<[149]>;
295 def SSR : Rs<6, "ssr", ["s6"]>, DwarfRegNum<[150]>;
296 def CCR : Rs<7, "ccr", ["s7"]>, DwarfRegNum<[151]>;
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H A DHexagonPatternsHVX.td333 def V60splatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
339 def V62splatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatb $Rs)>;
340 def V62splatrh: OutPatFrag<(ops node:$Rs), (V6_lvsplath $Rs)>;
341 def V62splatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
354 def: Pat<(VecI8 (splat_vector I32:$Rs)), (V60splatrb $Rs)>;
355 def: Pat<(VecI16 (splat_vector I32:$Rs)), (V60splatrh $Rs)>;
356 def: Pat<(VecI32 (splat_vector I32:$Rs)), (V60splatrw $Rs)>;
374 def: Pat<(VecI8 (splat_vector I32:$Rs)), (V62splatrb $Rs)>;
375 def: Pat<(VecI16 (splat_vector I32:$Rs)), (V62splatrh $Rs)>;
376 def: Pat<(VecI32 (splat_vector I32:$Rs)), (V62splatrw $Rs)>;
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H A DHexagonConstExtenders.cpp293 Register Rs; member
304 return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg; in operator ==()
310 if (Rs != Ex.Rs) in operator <()
311 return Rs < Ex.Rs; in operator <()
446 : Rs(R), HRI(I) {} in PrintRegister()
447 HCE::Register Rs; member
453 if (P.Rs.Reg != 0) in operator <<()
454 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); in operator <<()
471 OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); in operator <<()
1505 Register Rs = ExtI.second.Rs; // Only one reg allowed now. in calculatePlacement() local
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H A DHexagonIntrinsicsV5.td41 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
45 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
50 // Rdd=vpmpyh(Rs,Rt)
52 // Rxx[^]=vpmpyh(Rs,Rt)
56 // Rdd=pmpyw(Rs,Rt)
58 // Rxx^=pmpyw(Rs,Rt)
302 // Rd=[cround|round](Rs,Rt)[:sat]
303 // Rd=[cround|round](Rs,#u5)[:sat]
328 // Rdd=vmpyb[s]u(Rs,Rt)
332 // Rxx+=vmpyb[s]u(Rs,Rt)
H A DHexagonSplitDouble.cpp147 const USet &Rs = I.second; in isInduction() local
148 if (Rs.find(Reg) != Rs.end()) in isInduction()
376 return profit(Rs) + profit(Rt); in profit()
476 USet &Rs) { in collectIndRegsForLoop() argument
560 Rs.insert(DP.begin(), End); in collectIndRegsForLoop()
561 Rs.insert(CmpR1); in collectIndRegsForLoop()
562 Rs.insert(CmpR2); in collectIndRegsForLoop()
580 USet Rs; in collectIndRegs() local
582 Rs.clear(); in collectIndRegs()
583 collectIndRegsForLoop(L, Rs); in collectIndRegs()
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H A DHexagonPseudo.td42 class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp,
51 let Inst{27} = Rs;
209 def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs),
210 "callr $Rs", [], "", J2_callr.Itinerary, TypeJ>, OpcodeHexagon {
211 bits<5> Rs;
217 let Inst{20-16} = Rs;
336 (ins IntRegs:$Rs, u32_0Imm:$A), "", []>;
355 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
448 (ins IntRegs:$Rs, s32_0Imm:$Off, HvxQR:$Qt), "", []>,
469 (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>,
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H A DHexagonGenInsert.cpp128 RegisterSet &insert(const RegisterSet &Rs) { in insert()
129 return static_cast<RegisterSet&>(BitVector::operator|=(Rs)); in insert()
131 RegisterSet &remove(const RegisterSet &Rs) { in remove()
132 return static_cast<RegisterSet&>(BitVector::reset(Rs)); in remove()
155 bool includes(const RegisterSet &Rs) const { in includes()
157 return !Rs.BitVector::test(*this); in includes()
159 bool intersects(const RegisterSet &Rs) const { in intersects()
160 return BitVector::anyCommon(Rs); in intersects()
1211 void stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero,
1248 void IFOrdering::stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero, in stats() argument
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp201 MCOperand Rs, Rt; in getCompoundInsn() local
223 Rs = L.getOperand(1); in getCompoundInsn()
229 CompoundInsn->addOperand(Rs); in getCompoundInsn()
236 Rs = L.getOperand(1); in getCompoundInsn()
242 CompoundInsn->addOperand(Rs); in getCompoundInsn()
249 Rs = L.getOperand(1); in getCompoundInsn()
262 Rs = L.getOperand(1); in getCompoundInsn()
283 Rs = L.getOperand(1); in getCompoundInsn()
301 Rs = L.getOperand(1); in getCompoundInsn()
311 Rs = L.getOperand(1); in getCompoundInsn()
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/llvm-project-15.0.7/clang/test/Sema/
H A Dbuiltins-hexagon-v65.c5 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60() argument
6 return __builtin_HEXAGON_S6_rol_i_r(Rs, 3); in builtin_needs_v60()
9 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62() argument
10 return __builtin_HEXAGON_S6_vsplatrbp(Rs); in builtin_needs_v62()
H A Dbuiltins-hexagon-v55.c7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60() argument
9 return __builtin_HEXAGON_S6_rol_i_r(Rs, 3); in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62() argument
16 return __builtin_HEXAGON_S6_vsplatrbp(Rs); in builtin_needs_v62()
H A Dbuiltins-hexagon-v60.c7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60() argument
9 return __builtin_HEXAGON_S6_rol_i_r(Rs, 3); in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62() argument
16 return __builtin_HEXAGON_S6_vsplatrbp(Rs); in builtin_needs_v62()
H A Dbuiltins-hexagon-v62.c7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60() argument
9 return __builtin_HEXAGON_S6_rol_i_r(Rs, 3); in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62() argument
16 return __builtin_HEXAGON_S6_vsplatrbp(Rs); in builtin_needs_v62()
/llvm-project-15.0.7/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp618 if (Rs >= Rt) { in DecodeAddiGroupBranch()
621 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
646 if (Rs >= Rt) { in DecodePOP35GroupBranchMMR6()
653 } else if (Rs != 0 && Rs < Rt) { in DecodePOP35GroupBranchMMR6()
691 if (Rs >= Rt) { in DecodeDaddiGroupBranch()
694 } else if (Rs != 0 && Rs < Rt) { in DecodeDaddiGroupBranch()
719 if (Rs >= Rt) { in DecodePOP37GroupBranchMMR6()
726 } else if (Rs != 0 && Rs < Rt) { in DecodePOP37GroupBranchMMR6()
763 else if (Rs == 0) in DecodePOP65GroupBranchMMR6()
802 else if (Rs == 0) in DecodePOP75GroupBranchMMR6()
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/llvm-project-15.0.7/clang-tools-extra/clangd/unittests/
H A DAnnotations.cpp44 std::vector<clangd::Range> Rs; in ranges() local
45 Rs.reserve(OffsetRanges.size()); in ranges()
47 Rs.push_back(toLSPRange(code(), R)); in ranges()
49 return Rs; in ranges()
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_mips.cpp40 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction() argument
43 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
H A Dxray_mips64.cpp41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction() argument
44 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
/llvm-project-15.0.7/llvm/unittests/Remarks/
H A DYAMLRemarksSerializerTest.cpp26 remarks::SerializerMode Mode, ArrayRef<remarks::Remark> Rs, in check() argument
41 for (const remarks::Remark &R : Rs) in check()
283 SmallVector<remarks::Remark, 2> Rs; in TEST() local
298 Rs.emplace_back(R.clone()); in TEST()
299 Rs.emplace_back(std::move(R)); in TEST()
300 check(remarks::Format::YAMLStrTab, remarks::SerializerMode::Standalone, Rs, in TEST()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode() argument
155 switch (Rs) { in DecodeSrcAddrMode()
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
184 return DecodeSrcAddrMode(Rs, As); in DecodeSrcAddrModeI()
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
190 return DecodeSrcAddrMode(Rs, As); in DecodeSrcAddrModeII()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DScalarEvolutionDivision.cpp147 SmallVector<const SCEV *, 2> Qs, Rs; in visitAddExpr() local
159 Rs.push_back(R); in visitAddExpr()
164 Remainder = Rs[0]; in visitAddExpr()
169 Remainder = SE.getAddExpr(Rs); in visitAddExpr()
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dunpredictable-MVN-arm.txt17 # MVN(S)<c> <Rd>, <Rm>, <type> <Rs>
21 # | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | Rs | 0|type | 1| Rm |
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1620 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1630 TmpInst.addOperand(Rs); in processInstruction()
1640 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1650 TmpInst.addOperand(Rs); in processInstruction()
1660 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1670 TmpInst.addOperand(Rs); in processInstruction()
1683 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1700 TmpInst.addOperand(Rs); in processInstruction()
1718 TmpInst.addOperand(Rs); in processInstruction()
1728 TmpInst.addOperand(Rs); in processInstruction()
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