293       Register Rs;  member
298       ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {}  in ExtExpr()
301         return Rs.Reg == 0;  in trivial()
304         return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg;  in operator ==()
310         if (Rs != Ex.Rs)  in operator <()
311           return Rs < Ex.Rs;  in operator <()
446       : Rs(R), HRI(I) {}  in PrintRegister()
447     HCE::Register Rs;  member
453     if (P.Rs.Reg != 0)  in operator <<()
454       OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);  in operator <<()
470     if (P.Ex.Rs.Reg != 0)  in operator <<()
471       OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);  in operator <<()
1172           ED.Expr.Rs = MI.getOperand(OpNum-1);  in recordExtender()
1175         ED.Expr.Rs = MI.getOperand(OpNum-2);  in recordExtender()
1198         ED.Expr.Rs = MI.getOperand(OpNum-1);  in recordExtender()
1203         ED.Expr.Rs = MI.getOperand(OpNum-1);  in recordExtender()
1207         ED.Expr.Rs = MI.getOperand(OpNum+1);  in recordExtender()
1211         ED.Expr.Rs = MI.getOperand(OpNum+1);  in recordExtender()
1462                       return Extenders[I].Expr.Rs.isSlot();  in assignInits()
1466       return ED.Expr.Rs.isSlot() == IsStack &&  in assignInits()
1505   Register Rs = ExtI.second.Rs;  // Only one reg allowed now.  in calculatePlacement()  local
1506   const MachineInstr *DefI = Rs.isVReg() ? MRI->getVRegDef(Rs.Reg) : nullptr;  in calculatePlacement()
1540   if (Ex.Rs.isSlot()) {  in insertInitializer()
1545               .add(MachineOperand(Ex.Rs))  in insertInitializer()
1548     assert((Ex.Rs.Reg == 0 || Ex.Rs.isVReg()) && "Expecting virtual register");  in insertInitializer()
1558                   .add(MachineOperand(Ex.Rs));  in insertInitializer()
1562                   .add(MachineOperand(Ex.Rs))  in insertInitializer()
1572                   .add(MachineOperand(Ex.Rs))  in insertInitializer()
1580           .add(MachineOperand(Ex.Rs))  in insertInitializer()
1781     assert(Ex.Rs == RegOp && EV == ImmOp && Ex.Neg != IsAddi &&  in replaceInstrExpr()
1802     Register Rs = MI.getOperand(IsSub ? 3 : 2);  in replaceInstrExpr()  local
1804     assert(EV == V && Rs == Ex.Rs && IsSub == Ex.Neg && "Initializer mismatch");  in replaceInstrExpr()