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Searched refs:Rev (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/clang/lib/Basic/Targets/
H A DSystemZ.cpp111 const auto Rev = in getISARevision() local
115 if (Rev == std::end(ISARevisions)) in getISARevision()
117 return Rev->ISARevisionID; in getISARevision()
122 for (const ISANameRevision &Rev : ISARevisions) in fillValidCPUList() local
123 Values.push_back(Rev.Name); in fillValidCPUList()
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/
H A Dversioninfo.test257 # GNU-NEXT: 0x0000: Rev: 1 Flags: none Index: 0 Cnt: 1 Name: VERSION1
258 # GNU-NEXT: 0x001c: Rev: 1 Flags: BASE Index: 0 Cnt: 1 Name: VERSION1
259 # GNU-NEXT: 0x0038: Rev: 1 Flags: WEAK Index: 0 Cnt: 1 Name: VERSION1
260 # GNU-NEXT: 0x0054: Rev: 1 Flags: INFO Index: 0 Cnt: 1 Name: VERSION1
261 # GNU-NEXT: 0x0070: Rev: 1 Flags: BASE | WEAK | INFO Index: 2 Cnt: 1 Name: VERSION1
262 # GNU-NEXT: 0x008c: Rev: 1 Flags: <unknown> Index: 3 Cnt: 3 Name: VERSION2
H A Dverdef-invalid.test156 # PAST-STRTAB-END-GNU-NEXT: 0x0000: Rev: 1 Flags: none Index: 0 Cnt: 1 Name: <invalid vda_nam…
/llvm-project-15.0.7/clang-tools-extra/clang-tidy/abseil/
H A DStringFindStartswithCheck.cpp95 bool Rev = FindFun->getName().contains("rfind"); in check() local
117 << Neg << Rev; in check()
/llvm-project-15.0.7/lldb/examples/test/
H A Dusage-lldb-loggings21 Last Changed Rev: 162228
82 Last Changed Rev: 162228
H A Dusage-pre-post-flight20 Last Changed Rev: 154730
/llvm-project-15.0.7/llvm/test/MC/Disassembler/X86/
H A Damd3dnow.txt4 # Pub no. 24594 - Rev. 3.25 - Dec 2017 - pgs.468-469
/llvm-project-15.0.7/llvm/lib/TableGen/
H A DSetTheory.cpp126 RotOp(bool Rev) : Reverse(Rev) {} in RotOp()
/llvm-project-15.0.7/libcxx/docs/Status/
H A DCxx14Papers.csv2 "`3346 <https://wg21.link/n3346>`__","LWG","Terminology for Container Element Requirements - Rev 1"…
H A DCxx20Papers.csv107 "`P0660R10 <https://wg21.link/P0660R10>`__","LWG","Stop Token and Joining Thread, Rev 10","Cologne"…
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsDSPInstrInfo.td415 // microMIPS DSP Rev 1
532 // microMIPS DSP Rev 2
595 // microMIPS DSP Rev 3
H A DMipsDSPInstrInfo.td553 // MIPS DSP Rev 1
942 // MIPS DSP Rev 2
1113 // MIPS DSP Rev 1
1232 // MIPS DSP Rev 2
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleE500.td13 // Freescale Document Number E500MCRM, Rev. 1, 03/2012.
H A DPPCScheduleE500mc.td13 // Freescale Document Number E500MCRM, Rev. 1, 03/2012.
H A DPPCScheduleE5500.td13 // Freescale Document Number e5500RM, Rev. 1, 03/2012.
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp512 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer); in getSingleInstruction() local
514 Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0; in getSingleInstruction()
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DBuiltinsMips.def16 // MIPS DSP Rev 1
126 // MIPS DSP Rev 2
/llvm-project-15.0.7/clang/utils/TableGen/
H A DNeonEmitter.cpp1585 class Rev : public SetTheory::Operator { in emitDagShuffle() class
1589 Rev(unsigned ElementSize) : ElementSize(ElementSize) {} in emitDagShuffle() function in Intrinsic::DagEmitter::emitDagShuffle::Rev
1642 std::make_unique<Rev>(Arg1.first.getElementSizeInBits())); in emitDagShuffle()
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsMips.td22 // MIPS DSP Rev 1
273 // MIPS DSP Rev 2
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp10164 SDValue Rev = DAG.getNode(RevOpcode, dl, VT, Op0); in LowerVecReduce() local
10165 Op0 = DAG.getNode(BaseOpcode, dl, VT, Op0, Rev); in LowerVecReduce()
16461 auto isVMOVNShuffle = [&](ShuffleVectorSDNode *SVN, bool Rev) { in PerformSplittingToNarrowingStores() argument
16467 unsigned Off0 = Rev ? NumElts : 0; in PerformSplittingToNarrowingStores()
16468 unsigned Off1 = Rev ? 0 : NumElts; in PerformSplittingToNarrowingStores()
18506 unsigned Rev = VT == MVT::v4i32 ? ARMISD::VREV32 : ARMISD::VREV16; in PerformMVEExtCombine() local
18521 V0 = Extend(DAG.getNode(Rev, DL, SVN->getValueType(0), Op0)); in PerformMVEExtCombine()
18525 V0 = Extend(DAG.getNode(Rev, DL, SVN->getValueType(0), Op1)); in PerformMVEExtCombine()
18530 V1 = Extend(DAG.getNode(Rev, DL, SVN->getValueType(0), Op1)); in PerformMVEExtCombine()
18534 V1 = Extend(DAG.getNode(Rev, DL, SVN->getValueType(0), Op0)); in PerformMVEExtCombine()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp10522 SDValue Rev = DAG.getNode(AArch64ISD::REV64, dl, VT, V1); in LowerVECTOR_SHUFFLE() local
10523 return DAG.getNode(AArch64ISD::EXT, dl, VT, Rev, Rev, in LowerVECTOR_SHUFFLE()