| /llvm-project-15.0.7/llvm/lib/MCA/ |
| H A D | CodeEmitter.cpp | 25 MCInst Relaxed(Sequence[MCID]); in getOrCreateEncodingInfo() local
27 MAB.relaxInstruction(Relaxed, STI); in getOrCreateEncodingInfo()
30 MCE.encodeInstruction(Relaxed, VecOS, Fixups, STI); in getOrCreateEncodingInfo()
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| /llvm-project-15.0.7/lld/test/ELF/ |
| H A D | x86-64-tls-ie.s | 65 ## Relaxed to TLS IE. Share the GOT entry with GOTTPOFF.
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| H A D | riscv-relax-call-intra-sec.s | 34 ## Relaxed to jal. If we don't compute the precise value of a, we may consider
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| /llvm-project-15.0.7/llvm/test/MC/RISCV/ |
| H A D | scoped-relaxation.s | 14 # Relaxed reference, this will resolve to a pair of `RISCV_ADD64` and
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| /llvm-project-15.0.7/llvm/lib/MC/ |
| H A D | MCObjectStreamer.cpp | 450 MCInst Relaxed = Inst; in emitInstructionImpl() local
451 while (Backend.mayNeedRelaxation(Relaxed, STI)) in emitInstructionImpl()
452 Backend.relaxInstruction(Relaxed, STI); in emitInstructionImpl()
453 emitInstToData(Relaxed, STI); in emitInstructionImpl()
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| H A D | MCAssembler.cpp | 990 MCInst Relaxed = F.getInst(); in relaxInstruction() local
991 getBackend().relaxInstruction(Relaxed, *F.getSubtargetInfo()); in relaxInstruction()
1000 getEmitter().encodeInstruction(Relaxed, VecOS, Fixups, *F.getSubtargetInfo()); in relaxInstruction()
1003 F.setInst(Relaxed); in relaxInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86AsmBackend.cpp | 843 MCInst Relaxed = RF.getInst(); in padInstructionViaRelaxation() local
844 relaxInstruction(Relaxed, *RF.getSubtargetInfo()); in padInstructionViaRelaxation()
849 Emitter.encodeInstruction(Relaxed, VecOS, Fixups, *RF.getSubtargetInfo()); in padInstructionViaRelaxation()
856 RF.setInst(Relaxed); in padInstructionViaRelaxation()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | relaxed-fp-atomics.ll | 1 ; PR52927: Relaxed atomics can load to/store from fp regs directly
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| /llvm-project-15.0.7/flang/lib/Parser/ |
| H A D | openmp-parsers.cpp | 254 "RELAXED" >> construct<OmpClause>(construct<OmpClause::Relaxed>()) ||
350 "RELAXED" >> construct<OmpClause>(construct<OmpClause::Relaxed>())))))
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IntrinsicsWebAssembly.td | 222 // Relaxed SIMD intrinsics (experimental)
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| /llvm-project-15.0.7/clang/include/clang/Basic/ |
| H A D | BuiltinsWebAssembly.def | 164 // Relaxed SIMD builtins (experimental)
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrSIMD.td | 1337 // Relaxed swizzle
1347 // Relaxed floating-point to int conversions
1367 // Relaxed Fused Multiply- Add and Subtract (FMA/FMS)
1407 // Relaxed floating-point min and max.
1430 // Relaxed rounding q15 multiplication
1438 // Relaxed integer dot product
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| /llvm-project-15.0.7/flang/lib/Lower/ |
| H A D | OpenMP.cpp | 1279 } else if (std::get_if<Fortran::parser::OmpClause::Relaxed>( in genOmpAtomicHintAndMemoryOrderClauses()
1282 firOpBuilder.getContext(), omp::ClauseMemoryOrderKind::Relaxed); in genOmpAtomicHintAndMemoryOrderClauses()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/ |
| H A D | irtranslator-extract-used-by-dbg.ll | 138 !110 = !DIEnumerator(name: "Relaxed", value: 0)
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| /llvm-project-15.0.7/mlir/lib/Target/LLVMIR/Dialect/OpenMP/ |
| H A D | OpenMPToLLVMIRTranslation.cpp | 995 case omp::ClauseMemoryOrderKind::Relaxed: in convertAtomicOrdering()
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| /llvm-project-15.0.7/flang/lib/Semantics/ |
| H A D | check-omp-structure.cpp | 1841 CHECK_SIMPLE_CLAUSE(Relaxed, OMPC_relaxed) in CHECK_SIMPLE_CLAUSE()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.td | 651 // * 'Relaxed' immediates are supersets of the corresponding unsigned immediate.
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