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Searched refs:RegType (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td5754 [(set (AccumType RegType:$dst),
5755 (OpNode (AccumType RegType:$Rd),
5756 (InputType RegType:$Rn),
5777 [(set (AccumType RegType:$dst),
8074 …: BaseSIMDThreeSameVectorTied<Q, U, 0b010, 0b11111, RegType, asm, kind1, [(set (AccumType RegType:…
8097 RegType, RegType, V128, VectorIndexS,
8099 [(set (AccumType RegType:$dst),
8215 BaseSIMDIndexedTied<Q, U, 0b0, size, {0b111, Mixed}, RegType, RegType, V128,
8217 [(set (AccumType RegType:$dst),
8243 BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, RegType, RegType, V128,
[all …]
H A DAArch64FrameLowering.cpp2483 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enum
H A DAArch64InstrInfo.td1040 string rhs_kind, RegisterOperand RegType,
1043 lhs_kind, rhs_kind, RegType, AccumType,
1045 let Pattern = [(set (AccumType RegType:$dst),
1046 (AccumType (int_aarch64_neon_usdot (AccumType RegType:$Rd),
1050 (InputType RegType:$Rn))))];
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7024 MVT RegType = TLI->getPreferredSwitchConditionType(Context, OldVT); in optimizeSwitchType() local
7025 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchType()
7044 if (TLI->isSExtCheaperThanZExt(OldVT, RegType)) in optimizeSwitchType()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp3435 char RegType = RegTypes[RegNo / 8]; in getRegForInlineAsmConstraint() local
3437 char Tmp[] = {'{', RegType, RegIndex, '}', 0}; in getRegForInlineAsmConstraint()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td223 // RegType - Specify the list ValueType of the registers in this register