| /llvm-project-15.0.7/bolt/lib/Passes/ |
| H A D | RegAnalysis.cpp | 143 void RegAnalysis::getInstUsedRegsList(const MCInst &Inst, BitVector &RegSet, in getInstUsedRegsList() argument
147 BC.MIB->getClobberedRegs(Inst, RegSet); in getInstUsedRegsList()
149 BC.MIB->getUsedRegs(Inst, RegSet); in getInstUsedRegsList()
155 beConservative(RegSet); in getInstUsedRegsList()
162 beConservative(RegSet); in getInstUsedRegsList()
171 beConservative(RegSet); in getInstUsedRegsList()
177 RegSet |= BV->second; in getInstUsedRegsList()
186 RegSet |= BV->second; in getInstUsedRegsList()
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| /llvm-project-15.0.7/lldb/source/Plugins/Process/Linux/ |
| H A D | NativeRegisterContextLinux_x86_64.cpp | 712 if (IsCPUFeatureAvailable(RegSet::avx)) { in ReadAllRegisterValues()
844 RegSet feature_code) const { in IsCPUFeatureAvailable()
850 case RegSet::gpr: in IsCPUFeatureAvailable()
851 case RegSet::fpu: in IsCPUFeatureAvailable()
871 switch (static_cast<RegSet>(set_index)) { in IsRegisterSetAvailable()
872 case RegSet::gpr: in IsRegisterSetAvailable()
873 case RegSet::fpu: in IsRegisterSetAvailable()
875 case RegSet::avx: in IsRegisterSetAvailable()
877 case RegSet::mpx: in IsRegisterSetAvailable()
912 if (!IsCPUFeatureAvailable(RegSet::avx)) in IsAVX()
[all …]
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| H A D | NativeRegisterContextLinux_x86_64.h | 68 enum class RegSet { gpr, fpu, avx, mpx }; enum
109 bool IsCPUFeatureAvailable(RegSet feature_code) const;
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiDelaySlotFiller.cpp | 68 bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
253 bool Filler::isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) { in isRegInSet() argument
256 if (RegSet.count(*AI)) in isRegInSet()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | RegisterPressure.h | 273 using RegSet = SparseSet<IndexMaskPair>; variable
274 RegSet Regs;
296 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
319 RegSet::iterator I = Regs.find(SparseIndex); in erase()
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| /llvm-project-15.0.7/bolt/include/bolt/Passes/ |
| H A D | RegAnalysis.h | 45 void getInstUsedRegsList(const MCInst &Inst, BitVector &RegSet,
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | DelaySlotFiller.cpp | 74 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
344 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) in IsRegInSet() argument
349 if (RegSet.count(*AI)) in IsRegInSet()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsDelaySlotFiller.cpp | 133 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
445 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const { in isRegInSet() argument
448 if (RegSet.test(*AI)) in isRegInSet()
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| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 37 const uint8_t *const RegSet; variable
74 return (RegSet[Byte] & (1 << InByte)) != 0; in contains()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 113 using RegSet = DenseSet<Register>; typedef
122 RegSet regsLive;
146 RegSet regsKilled;
150 RegSet regsLiveOut;
154 RegSet vregsPassed;
158 RegSet vregsRequired;
176 bool addRequired(const RegSet &RS) { in addRequired()
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| H A D | RegAllocPBQP.cpp | 149 using RegSet = std::set<Register>; typedef in __anon76ec55000111::RegAllocPBQP
153 RegSet VRegsToAlloc, EmptyIntervalVRegs;
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| H A D | AggressiveAntiDepBreaker.cpp | 259 SmallSet<unsigned, 4> RegSet; in AntiDepEdges() local
262 if (RegSet.insert(Pred.getReg()).second) in AntiDepEdges()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 211 void updateLiveness(std::set<Register> &RegSet, bool Recalc,
552 void HexagonExpandCondsets::updateLiveness(std::set<Register> &RegSet, in updateLiveness() argument
556 for (Register R : RegSet) { in updateLiveness()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | Thumb1FrameLowering.cpp | 862 const std::set<Register> &RegSet) { in getNextOrderedReg() argument
864 [&](Register Reg) { return RegSet.count(Reg); }); in getNextOrderedReg()
|