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Searched refs:RegOp0 (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp93 unsigned RegOp0 = Inst.getOperand(0).getReg(); in LowerCompactBranch() local
96 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch()
115 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp972 MachineOperand RegOp0 = getLdStRegOp(*RtMI); in mergePairedInsns() local
975 if (RegOp0.isUse()) { in mergePairedInsns()
981 RegOp0.setIsKill(false); in mergePairedInsns()
1001 MIB.add(RegOp0) in mergePairedInsns()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp4135 Register RegOp0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() local
4136 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp0) in EmitInstrWithCustomInserter()
4138 Src0.setReg(RegOp0); in EmitInstrWithCustomInserter()