| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 66 memset(RegMap, 0, sizeof(RegMap)); in FPS()
164 unsigned RegMap[NumFPRegs]; member
186 return RegMap[RegNo]; in getSlot()
214 RegMap[Reg] = StackTop++; in pushReg()
233 std::swap(RegMap[RegNo], RegMap[RegOnTop]); in moveToTop()
236 if (RegMap[RegOnTop] >= StackTop) in moveToTop()
908 RegMap[TopReg] = OldSlot; in freeStackSlotBefore()
909 RegMap[FPRegNo] = ~0; in freeStackSlotBefore()
939 std::swap(RegMap[KReg], RegMap[DReg]); in adjustLiveRegs()
1444 RegMap[Dest] = UpdatedSlot; in handleTwoArgFP()
[all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 423 DenseMap<Register, Register> &RegMap) { in getMappedReg() argument
425 DenseMap<Register, Register>::iterator SI = RegMap.find(Reg); in getMappedReg()
426 if (SI == RegMap.end()) in getMappedReg()
447 DenseMap<Register, Register> &RegMap, in removeMapRegEntry() argument
454 for (auto SI : RegMap) { in removeMapRegEntry()
468 RegMap.erase(SrcReg); in removeMapRegEntry()
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| H A D | MachineVerifier.cpp | 114 using RegMap = DenseMap<Register, const MachineInstr *>; typedef
142 RegMap vregsLiveIn;
184 bool addRequired(const RegMap &RM) { in addRequired()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1385 using RegMap = std::map<const CodeGenRegister*, const CodeGenRegister*>; in computeComposites() typedef
1390 std::map<const CodeGenSubRegIndex*, RegMap> SubRegAction; in computeComposites()
1401 RegMap C; in computeComposites()
1402 const RegMap &Img1 = SubRegAction.at(Sub1); in computeComposites()
1403 const RegMap &Img2 = SubRegAction.at(Sub2); in computeComposites()
1413 auto agree = [] (const RegMap &Map1, const RegMap &Map2) { in computeComposites()
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXAsmPrinter.cpp | 290 DenseMap<unsigned, unsigned> &RegMap = VRegMapping[RC]; in encodeVirtualRegister() local
291 unsigned RegNum = RegMap[Reg]; in encodeVirtualRegister()
586 const DenseMap<unsigned, unsigned> &RegMap = I->second; in getVirtualRegisterName() local
588 VRegMap::const_iterator VI = RegMap.find(Reg); in getVirtualRegisterName()
589 assert(VI != RegMap.end() && "Bad virtual register"); in getVirtualRegisterName()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 1381 UnsignedMap RegMap; in generateInserts() local
1386 RegMap[VR] = NewVR; in generateInserts()
1396 unsigned NewR = RegMap[I.first]; in generateInserts()
1428 MRI->replaceRegWith(I.first, RegMap[I.first]); in generateInserts()
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| H A D | HexagonBitSimplify.cpp | 3104 DenseMap<unsigned,unsigned> RegMap; in moveGroup() local
3113 RegMap.insert(std::make_pair(G.Inp.Reg, PhiR)); in moveGroup()
3130 unsigned UseR = RegMap[Op.getReg()]; in moveGroup()
3133 RegMap.insert(std::make_pair(DR, NewDR)); in moveGroup()
3136 HBS::replaceReg(OldPhiR, RegMap[G.Out.Reg], *MRI); in moveGroup()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 229 } RegMap[] = { in initLLVMToCVRegMapping() local
330 for (const auto &I : RegMap) in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 71 } RegMap[] = { in initLLVMToCVRegMapping() local
299 for (const auto &I : RegMap) in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 178 } RegMap[] = { in initLLVMToSEHAndCVRegMapping() local
385 for (const auto &I : RegMap) in initLLVMToSEHAndCVRegMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 2049 RegMap = { in ComputeRegsForAlias() local
2069 std::vector<unsigned> Regs = RegMap[std::make_pair(ElementWidth, Reg)]; in ComputeRegsForAlias()
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