Searched refs:RegLR (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 293 MCOperand RegLR = MCOperand::createReg(VE::SX10); // LR in lowerGETTLSAddrAndEmitMCInsts() local
312 emitSIC(*OutStreamer, RegLR, STI); in lowerGETTLSAddrAndEmitMCInsts()
315 emitLEASLrri(*OutStreamer, RegS0, RegLR, hiImm, RegS0, STI); in lowerGETTLSAddrAndEmitMCInsts()
323 emitLEASLrri(*OutStreamer, RegS12, RegLR, hiImm2, RegS12, STI); in lowerGETTLSAddrAndEmitMCInsts()
324 emitBSIC(*OutStreamer, RegLR, RegS12, STI); in lowerGETTLSAddrAndEmitMCInsts()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 39 RegLR = 3 enumerator
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| H A D | ARMBaseRegisterInfo.cpp | 351 case ARMRI::RegLR: in getRegAllocationHints()
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| H A D | MVETPAndVPTOptimisationsPass.cpp | 1048 MF->getRegInfo().setRegAllocationHint(R, ARMRI::RegLR, 0); in HintDoLoopStartReg()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | RegisterCoalescer.cpp | 3771 LiveRange &RegLR, in checkMergingChangesDbgValuesImpl() argument
3787 auto ShouldUndef = [&RegVals, &RegLR, &LastUndefResult, in checkMergingChangesDbgValuesImpl()
3799 auto OtherIt = RegLR.find(Idx); in checkMergingChangesDbgValuesImpl()
3800 if (OtherIt == RegLR.end()) in checkMergingChangesDbgValuesImpl()
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