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Searched refs:RegKind (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp110 unsigned &RegKind);
1053 unsigned RegNo, RegKind; in parseOperand() local
1112 unsigned RegKind; in parseSparcAsmOperand() local
1210 RegKind = SparcOperand::rk_None; in matchRegisterName()
1217 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1223 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1315 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1322 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1328 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1334 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp122 unsigned RegKind : 4; member
193 Op->Mem.RegKind = RegKind; in createMem()
226 bool isReg(RegisterKind RegKind) const { in isReg()
227 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
267 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
268 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
276 bool isMemDisp12Len4(RegisterKind RegKind) const { in isMemDisp12Len4()
279 bool isMemDisp12Len8(RegisterKind RegKind) const { in isMemDisp12Len8()
438 RegisterKind RegKind);
1110 RegisterKind RegKind) { in parseAddress() argument
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp67 enum class RegKind { enum
266 template <RegKind VectorKind>
362 RegKind Kind;
401 RegKind RegisterKind;
1163 RegKind RK; in isSVEVectorReg()
2004 assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector || in CreateVectorReg()
2380 case RegKind::NeonVector: in parseVectorKind()
2408 case RegKind::SVEDataVector: in parseVectorKind()
2409 case RegKind::Matrix: in parseVectorKind()
3971 template <RegKind VectorKind>
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1221 switch (RegKind) { in usesRegister()
2485 switch (RegKind) { in AddNextRegisterToList()
2610 assert(isRegularReg(RegKind)); in getRegularReg()
2613 if (RegKind == IS_SGPR || RegKind == IS_TTMP) { in getRegularReg()
2625 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg()
2691 RegKind = IS_SPECIAL; in ParseSpecialReg()
2714 RegKind = RI->Kind; in ParseRegularReg()
2767 if (NextRegKind != RegKind) { in ParseRegList()
2780 if (isRegularReg(RegKind)) in ParseRegList()
2837 switch (RegKind) { in getGprCountSymbolName()
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/llvm-project-15.0.7/lldb/source/Plugins/ABI/X86/
H A DABIX86.cpp37 enum RegKind { enum
51 RegKind subreg_kind;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.h31 enum RegKind { enum
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td539 = "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";
551 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
561 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
1007 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
1009 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp449 bool validateMSAIndex(int Val, int RegKind);
801 enum RegKind { enum in __anon03c4d4620211::MipsOperand
859 RegKind Kind; /// Bitfield of the kinds it could possibly be
889 RegKind RegKind, in CreateReg() argument
896 Op->RegIdx.Kind = RegKind; in CreateReg()
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DLoopVectorize.cpp5159 TargetTransformInfo::RegisterKind RegKind = in getMaximizedVFForTarget() local
5164 TTI.shouldMaximizeVectorBandwidth(RegKind))) { in getMaximizedVFForTarget()