Home
last modified time | relevance | path

Searched refs:RegInfos (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/
H A DControlHeightReduction.cpp141 RegInfos.push_back(RI); in CHRScope()
185 RegInfos.append(Next->RegInfos.begin(), Next->RegInfos.end()); in append()
192 for (RegInfo &RI : RegInfos) in addSub()
225 RegInfos, in split()
234 RegInfos.erase(BoundaryIt, RegInfos.end()); in split()
439 if (RegInfos[0].R->getParent()) { in print()
1140 SmallVector<RegInfo, 8> RegInfos(Scope->RegInfos); // Copy in splitScope() local
1141 for (RegInfo &RI : RegInfos) { in splitScope()
1150 if (RI.R == RegInfos[0].R) { in splitScope()
1412 return Scope1->RegInfos[0].R->getDepth() < Scope2->RegInfos[0].R->getDepth(); in CHRScopeSorter()
[all …]
/llvm-project-15.0.7/lldb/unittests/tools/lldb-server/tests/
H A DMessageObjects.cpp73 ArrayRef<RegisterInfo> RegInfos) { in parseRegisters() argument
87 parseRegisterValue(RegInfos[Register], ValueStr, support::big); in parseRegisters()
96 ArrayRef<RegisterInfo> RegInfos) { in create() argument
124 auto RegsOr = parseRegisters(*register_dict, RegInfos); in create()
228 ArrayRef<RegisterInfo> RegInfos) { in create() argument
232 return StopReplyStop::create(Response, Endian, RegInfos); in create()
240 support::endianness Endian, ArrayRef<lldb_private::RegisterInfo> RegInfos) { in parseRegisters() argument
257 auto RegValOr = parseRegisterValue(RegInfos[Reg], Val[0], Endian); in parseRegisters()
267 ArrayRef<RegisterInfo> RegInfos) { in create() argument
299 const RegisterInfo *PcInfo = find_if(RegInfos, [](const RegisterInfo &Info) { in create()
[all …]
H A DMessageObjects.h68 llvm::ArrayRef<lldb_private::RegisterInfo> RegInfos);
75 llvm::ArrayRef<lldb_private::RegisterInfo> RegInfos);
98 llvm::ArrayRef<lldb_private::RegisterInfo> RegInfos);
118 llvm::ArrayRef<lldb_private::RegisterInfo> RegInfos);
135 llvm::ArrayRef<lldb_private::RegisterInfo> RegInfos);
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td134 let RegInfos = XLenRI;
138 let RegInfos = XLenRI;
142 let RegInfos = XLenRI;
146 let RegInfos = XLenRI;
154 let RegInfos = XLenRI;
161 let RegInfos = XLenRI;
173 let RegInfos = XLenRI;
177 let RegInfos = XLenRI;
467 let RegInfos = XLenRI;
544 let RegInfos = XLenRI in {
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRDFRegisters.cpp30 RegInfos.resize(TRI.getNumRegs()); in PhysicalRegisterInfo()
35 RegInfo &RI = RegInfos[R]; in PhysicalRegisterInfo()
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
176 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
236 const RegInfo &RI = RegInfos[R]; in mapTo()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td97 let RegInfos = GRLenRI;
152 let RegInfos = GRLenRI;
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRDFRegisters.h158 std::vector<RegInfo> RegInfos; member
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td509 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
515 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
521 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
527 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td221 RegInfoByHwMode RegInfos;