| /llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 115 if (!RegID) in onInstructionExecuted()
123 if (RenameAs && RenameAs != RegID) in onInstructionExecuted()
124 RegID = RenameAs; in onInstructionExecuted()
231 MCPhysReg RegID = WS.getRegisterID(); in addRegisterWrite() local
235 if (!RegID) in addRegisterWrite()
263 RegID = RRI.RenameAs; in addRegisterWrite()
343 if (!RegID) in removeRegisterWrite()
352 if (RenameAs && RenameAs != RegID) { in removeRegisterWrite()
353 RegID = RenameAs; in removeRegisterWrite()
510 assert(RegID && RegID < RegisterMappings.size()); in collectWrites()
[all …]
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| /llvm-project-15.0.7/llvm/lib/MCA/ |
| H A D | Instruction.cpp | 21 void WriteState::writeStartEvent(unsigned IID, MCPhysReg RegID, in writeStartEvent() argument
24 CRD.RegID = RegID; in writeStartEvent()
30 void ReadState::writeStartEvent(unsigned IID, MCPhysReg RegID, in writeStartEvent() argument
43 CRD.RegID = RegID; in writeStartEvent()
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| H A D | InstrBuilder.cpp | 691 MCPhysReg RegID = 0; in createInstruction() local
700 RegID = Op.getReg(); in createInstruction()
703 RegID = RD.RegisterID; in createInstruction()
707 if (!RegID) in createInstruction()
713 NewIS->getUses()[Idx] = ReadState(RD, RegID); in createInstruction()
716 NewIS->getUses().emplace_back(RD, RegID); in createInstruction()
765 RegID = WD.isImplicitWrite() ? WD.RegisterID in createInstruction()
768 if (WD.IsOptionalDef && !RegID) { in createInstruction()
773 assert(RegID && "Expected a valid register ID!"); in createInstruction()
776 WriteState(WD, RegID, in createInstruction()
[all …]
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| /llvm-project-15.0.7/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 187 MCPhysReg RegID; member
248 WriteState(const WriteDescriptor &Desc, MCPhysReg RegID,
250 : WD(&Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID), PRFID(0),
261 void setRegisterID(const MCPhysReg RegID) { RegisterID = RegID; } in setRegisterID() argument
303 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
356 ReadState(const ReadDescriptor &Desc, MCPhysReg RegID) in ReadState() argument
357 : RD(&Desc), RegisterID(RegID), PRFID(0), DependentWrites(0), in ReadState()
375 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
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| /llvm-project-15.0.7/llvm/tools/llvm-mca/Views/ |
| H A D | BottleneckAnalysis.h | 254 void addRegisterDep(unsigned From, unsigned To, unsigned RegID, in addRegisterDep() argument
256 addDependency(From, To, {DependencyEdge::DT_REGISTER, RegID, Cost}); in addRegisterDep()
316 void addRegisterDep(unsigned From, unsigned To, unsigned RegID, unsigned Cy);
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| H A D | BottleneckAnalysis.cpp | 453 unsigned RegID, unsigned Cost) { in addRegisterDep() argument
457 DG.addRegisterDep(From, To + SourceSize, RegID, Cost); in addRegisterDep()
458 DG.addRegisterDep(From + SourceSize, To + (SourceSize * 2), RegID, Cost); in addRegisterDep()
461 DG.addRegisterDep(From + SourceSize, To + SourceSize, RegID, Cost); in addRegisterDep()
522 addRegisterDep(From, To, RegDep.RegID, Cycles); in onEvent()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MLRegallocEvictAdvisor.cpp | 318 using RegID = unsigned; typedef in __anon8d2f77590111::MLEvictAdvisor
319 mutable DenseMap<RegID, LIFeatureComponents> CachedFeatures;
697 RegID ID = LI.reg().id(); in getLIFeatureComponents()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 537 auto ClearsSuperReg = [=](unsigned RegID) { in clearsSuperRegisters() argument
542 if (GR32RC.contains(RegID)) in clearsSuperRegisters()
553 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID); in clearsSuperRegisters()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6805 auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ? in LowerINTRINSIC_WO_CHAIN() local
6807 return getPreloadedValue(DAG, *MFI, VT, RegID); in LowerINTRINSIC_WO_CHAIN()
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