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Searched refs:RegI (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/IPO/
H A DCalledValuePropagation.cpp262 auto RegI = CVPLatticeKey(&CB, IPOGrouping::Register); in visitCallBase() local
275 ChangedValues[RegI] = getOverdefinedVal(); in visitCallBase()
296 ChangedValues[RegI] = in visitCallBase()
305 auto RegI = CVPLatticeKey(&I, IPOGrouping::Register); in visitSelect() local
308 ChangedValues[RegI] = in visitSelect()
318 auto RegI = CVPLatticeKey(&I, IPOGrouping::Register); in visitLoad() local
321 ChangedValues[RegI] = in visitLoad()
324 ChangedValues[RegI] = getOverdefinedVal(); in visitLoad()
351 auto RegI = CVPLatticeKey(&I, IPOGrouping::Register); in visitInst() local
352 ChangedValues[RegI] = getOverdefinedVal(); in visitInst()
[all …]
/llvm-project-15.0.7/llvm/unittests/Analysis/
H A DSparsePropagation.cpp164 auto RegI = TestLatticeKey(&I, IPOGrouping::Register); in visitCallBase() local
166 ChangedValues[RegI] = getOverdefinedVal(); in visitCallBase()
178 ChangedValues[RegI] = in visitCallBase()
179 MergeValues(SS.getValueState(RegI), SS.getValueState(RetF)); in visitCallBase()
217 auto RegI = TestLatticeKey(&I, IPOGrouping::Register); in visitInst() local
218 ChangedValues[RegI] = getOverdefinedVal(); in visitInst()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCWin64EH.cpp711 unsigned RegI = 0, RegF = 0; in tryARM64PackedUnwind() local
743 RegI = 2; in tryARM64PackedUnwind()
751 RegI += 1; in tryARM64PackedUnwind()
774 Inst.Register != 19 + RegI) in tryARM64PackedUnwind()
776 RegI += 2; in tryARM64PackedUnwind()
781 if (Inst.Register == 19 + RegI) in tryARM64PackedUnwind()
782 RegI += 1; in tryARM64PackedUnwind()
794 RegI += 1; in tryARM64PackedUnwind()
826 RegI += 2; in tryARM64PackedUnwind()
877 if (RegI > 10 || RegF > 8) in tryARM64PackedUnwind()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp373 auto RegI = getSavedReg(CSI, Which); in assignCalleeSavedSpillSlots() local
374 if (RegI == CSI.end() || RegI->getFrameIdx() == 0) { in assignCalleeSavedSpillSlots()
378 if (RegI != CSI.end()) in assignCalleeSavedSpillSlots()
379 RegI->setFrameIdx(FI); in assignCalleeSavedSpillSlots()
381 MFI.setObjectOffset(RegI->getFrameIdx(), CurOffset); in assignCalleeSavedSpillSlots()
/llvm-project-15.0.7/llvm/tools/llvm-readobj/
H A DARMWinEHPrinter.cpp1240 SW.printNumber("RegI", RF.RegI()); in dumpPackedARM64Entry()
1250 int IntSZ = 8 * RF.RegI(); in dumpPackedARM64Entry()
1277 if (RF.RegI() > 0 || RF.RegF() > 0 || RF.CR() == 1) { in dumpPackedARM64Entry()
1292 } else if (I == 0 && RF.RegI() == 0 && RF.CR() != 1) { in dumpPackedARM64Entry()
1300 if (RF.CR() == 1 && (RF.RegI() % 2) == 0) { in dumpPackedARM64Entry()
1301 if (RF.RegI() == 0) in dumpPackedARM64Entry()
1306 for (int I = (RF.RegI() + 1) / 2 - 1; I >= 0; I--) { in dumpPackedARM64Entry()
1307 if (I == (RF.RegI() + 1) / 2 - 1 && RF.RegI() % 2 == 1) { in dumpPackedARM64Entry()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp202 CodeGenRegister::Vec::const_iterator RegI, RegE; member in __anoncff4b8180111::RegUnitIterator
208 RegI(Regs.begin()), RegE(Regs.end()) { in RegUnitIterator()
210 if (RegI == RegE) { in RegUnitIterator()
214 UnitI = (*RegI)->getRegUnits().begin(); in RegUnitIterator()
215 UnitE = (*RegI)->getRegUnits().end(); in RegUnitIterator()
224 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; } in getReg()
236 if (++RegI == RegE) in advance()
238 UnitI = (*RegI)->getRegUnits().begin(); in advance()
239 UnitE = (*RegI)->getRegUnits().end(); in advance()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DARMWinEH.h264 uint8_t RegI() const { in RegI() function
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.cpp1864 for (_Iterator RegI = First; RegI != End; ++RegI) { in fillVgprSgprCost() local
1865 Register Reg = *RegI; in fillVgprSgprCost()