Searched refs:RegHi (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 461 Register RegHi = RegLo + 1; in LowerReturn() local
466 Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue); in LowerReturn()
468 RetOps.push_back(DAG.getRegister(RegHi, MVT::i32)); in LowerReturn()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2642 int64_t RegLo, RegHi; in ParseRegRange() local
2654 if (!parseExpr(RegHi)) in ParseRegRange()
2657 RegHi = RegLo; in ParseRegRange()
2668 if (!isUInt<32>(RegHi)) { in ParseRegRange()
2673 if (RegLo > RegHi) { in ParseRegRange()
2679 RegWidth = 32 * ((RegHi - RegLo) + 1); in ParseRegRange()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1841 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
1843 MIB.addReg(RegHi, Flags); in addExclusiveRegPair()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2099 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() local
2112 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) in expandPostRAPseudo()
2113 .addReg(RegHi); in expandPostRAPseudo()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11517 Register RegHi = RegLo + 1; in LowerReturn() local
11520 STI.isRegisterReservedByUser(RegHi)) in LowerReturn()
11528 Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue); in LowerReturn()
11530 RetOps.push_back(DAG.getRegister(RegHi, MVT::i32)); in LowerReturn()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4113 Register RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4() local
4115 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32); in LowerFormalArguments_32SVR4()
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