Home
last modified time | relevance | path

Searched refs:RegClassUnitSets (Results 1 – 2 of 2) sorted by relevance

/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.h596 std::vector<std::vector<unsigned>> RegClassUnitSets; variable
803 return RegClassUnitSets.size(); in getNumRegClassPressureSetLists()
811 return RegClassUnitSets[RCIdx]; in getRCPressureSetIDs()
H A DCodeGenRegisters.cpp1888 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets"); in pruneUnitSets()
2044 RegClassUnitSets.resize(RegClasses.size()); in computeRegUnitSets()
2069 RegClassUnitSets[RCIdx].push_back(USIdx); in computeRegUnitSets()
2073 assert((!RegClassUnitSets[RCIdx].empty() || !RC.GeneratePressureSet) && in computeRegUnitSets()
2091 for (unsigned e = RegClassUnitSets.size(); in computeRegUnitSets()
2093 if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) { in computeRegUnitSets()
2098 if (RCUnitSetsIdx == RegClassUnitSets.size()) { in computeRegUnitSets()
2100 RegClassUnitSets.resize(RCUnitSetsIdx + 1); in computeRegUnitSets()
2101 RegClassUnitSets[RCUnitSetsIdx].swap(RUSets); in computeRegUnitSets()