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Searched refs:RegClass (Results 1 – 25 of 87) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td389 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
403 wti.RegClass:$rd, GPR:$rs1, vti.RegClass:$rs2,
478 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
504 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
539 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
564 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
596 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
854 fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
859 fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
864 fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
[all …]
H A DRISCVInstrInfoVVLPatterns.td851 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
878 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
916 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
922 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
956 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1171 vti.RegClass:$rs2, vti.RegClass:$rs2, vti.RegClass:$rs1,
1375 fvti.RegClass:$rs2, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0),
1554 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
1588 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1,
1619 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
[all …]
H A DRISCVInstrInfoVPseudos.td3644 vti.RegClass, vti.RegClass>;
3654 vti.RegClass, vti.RegClass>;
3672 vti.RegClass, ivti.RegClass>;
3721 Vti.RegClass, Vti.RegClass>;
3748 Wti.RegClass, Wti.RegClass, Vti.RegClass>;
3760 Wti.RegClass, Vti.RegClass>;
3785 Wti.RegClass, Vti.RegClass>;
3822 vti.RegClass, vti.RegClass>;
3910 vti.RegClass, vti.RegClass>;
4106 wti.RegClass, vti.RegClass, vti.RegClass>;
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dget-operand-type.td14 def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
19 def RegOp : RegisterOperand<RegClass>;
41 let OutOperandList = (outs RegClass:$d);
55 // CHECK-NEXT: RegClass, RegOp,
H A DRegisterEncoder.td15 def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
17 def RegOperand : RegisterOperand<RegClass> {
H A DVarLenDecoder.td13 def RegClass : RegisterClass<"foo", [i64], 0, (add Reg)>;
15 def GR64 : RegisterOperand<RegClass>;
H A DVarLenEncoder.td15 def RegClass : RegisterClass<"foo", [i64], 0, (add Reg)>;
17 def GR64 : RegisterOperand<RegClass>;
H A DAliasAsmString.td13 def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
H A DAsmVariant.td26 def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
H A DMnemonicAlias.td12 def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.cpp33 const MCRegisterClass &RegClass) in RegisterAliasingTracker() argument
35 for (MCPhysReg PhysReg : RegClass) in RegisterAliasingTracker()
76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
78 Found.reset(new RegisterAliasingTracker(RegInfo, ReservedReg, RegClass)); in getRegisterClass()
H A DMCInstrDescView.cpp119 if (OpInfo.RegClass >= 0) in create()
120 Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass); in create()
274 &RegInfo.getRegClass(Op.Info->RegClass)) in dump()
H A DRegisterAliasing.h45 const MCRegisterClass &RegClass);
/llvm-project-15.0.7/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp104 if (MOI.RegClass == AVR::ZREGRegClassID) { in printOperand()
124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
126 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVMCCodeEmitter.cpp70 return (DefOpInfo->RegClass == SPIRV::IDRegClassID || in hasType()
71 DefOpInfo->RegClass == SPIRV::ANYIDRegClassID) && in hasType()
72 FirstArgOpInfo->RegClass == SPIRV::TYPERegClassID; in hasType()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRDFRegisters.cpp36 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
37 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
39 RI.RegClass = nullptr; in PhysicalRegisterInfo()
42 RI.RegClass = RC; in PhysicalRegisterInfo()
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
176 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
237 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
H A DRegisterClassInfo.cpp51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
107 RCInfo &RCI = RegClass[RC->getID()]; in compute()
H A DMachineRegisterInfo.cpp156 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
158 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
159 assert(RegClass->isAllocatable() && in createVirtualRegister()
164 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
99 CopyLocalOpc = WebAssembly::getCopyOpcodeForRegClass(RegClass); in maybeRewriteToFallthrough()
100 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
H A DWebAssemblyRegStackify.cpp105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
106 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
109 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
112 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
117 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
122 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
642 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
643 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
644 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
647 TII->get(getTeeOpcode(RegClass)), TeeReg) in moveAndTeeForMultiUse()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td554 RegisterClass RegClass = regclass;
644 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
654 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
661 [(set typeinfo.RegClass:$dst, EFLAGS,
662 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
669 [(set typeinfo.RegClass:$dst, EFLAGS,
670 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
677 (outs typeinfo.RegClass:$dst),
678 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
694 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h46 std::unique_ptr<RCInfo[]> RegClass; variable
80 const RCInfo &RCI = RegClass[RC->getID()]; in get()
H A DRegisterScavenging.h175 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
177 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterBanks.td10 // as InstructionSelector RegClass checking code relies on them
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1886 Register TrueBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1887 Register FalseBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1952 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
1953 Register NextDestReg = MRI->createVirtualRegister(RegClass); in insertChainedPHI()
2012 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2013 Register PHIDestReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2014 Register IfSourceReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2127 const TargetRegisterClass *RegClass = in createEntryPHI() local
2266 Register CodeBBSelectReg = MRI->createVirtualRegister(RegClass); in createIfRegion()
2402 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
[all …]

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