| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 560 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() argument
561 return isSuperRegister(RegB, RegA); in isSubRegister()
565 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
568 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq() argument
569 return isSuperRegisterEq(RegB, RegA); in isSubRegisterEq()
574 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq() argument
575 return RegA == RegB || isSuperRegister(RegA, RegB); in isSuperRegisterEq()
580 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq() argument
581 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); in isSuperOrSubRegisterEq()
585 bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 438 if (RegA == RegB) in regsAreCompatible()
440 if (!RegA || !RegB) in regsAreCompatible()
442 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
717 DstRegMap.erase(RegB); in convertInstTo3Addr()
1461 Register RegB = 0; in processTiedPairs() local
1475 if (RegA == RegB) { in processTiedPairs()
1501 MIB.addReg(RegB, 0, SubRegB); in processTiedPairs()
1593 SrcRegMap[LastCopiedReg] = RegB; in processTiedPairs()
1643 Register RegB = TO.first; in processStatepoint() local
1657 if (RegA == RegB) in processStatepoint()
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| H A D | ImplicitNullChecks.cpp | 293 Register RegB = MOB.getReg(); in canReorder() local
295 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
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| H A D | TargetInstrInfo.cpp | 843 Register RegB = OpB.getReg(); in reassociateOps() local
850 if (Register::isVirtualRegister(RegB)) in reassociateOps()
851 MRI.constrainRegClass(RegB, RC); in reassociateOps()
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| /llvm-project-15.0.7/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 126 bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const { in regsOverlap()
129 MCRegUnitIterator RUB(RegB, this); in regsOverlap()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 419 bool regsOverlap(Register RegA, Register RegB) const { in regsOverlap() argument
420 if (RegA == RegB) in regsOverlap()
422 if (RegA.isPhysical() && RegB.isPhysical()) in regsOverlap()
423 return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg()); in regsOverlap()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVModuleAnalysis.cpp | 201 Register RegB = B->getOperand(i).getReg(); in findSameInstrInMS() local
203 MAI.getRegisterAlias(B->getMF(), RegB); in findSameInstrInMS()
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| /llvm-project-15.0.7/llvm/unittests/Analysis/ |
| H A D | SparsePropagation.cpp | 480 auto RegB = TestLatticeKey(B, IPOGrouping::Register); in TEST_F() local
482 EXPECT_TRUE(Solver.getExistingValueState(RegB).isConstant()); in TEST_F()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 627 auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) { in isArgumentRegister() argument
628 return TRI.isSuperOrSubRegisterEq(RegA, RegB); in isArgumentRegister()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2210 for (auto &RegB : UsesB) { in isDependent() local
2212 if (RegA == RegB) in isDependent()
2217 if (RegB == *SubRegs) in isDependent()
2220 if (Register::isPhysicalRegister(RegB)) in isDependent()
2221 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 517 Register RegB = Root.getOperand(AddOpIdx).getReg(); in getFMAPatterns() local
518 MachineInstr *Prev = MRI->getUniqueVRegDef(RegB); in getFMAPatterns()
865 RegA21, RegB; in reassociateFMA() local
870 GetFMAInstrInfo(Root, RegM31, RegM32, RegB, KillM31, KillM32, KillB); in reassociateFMA()
1020 .addReg(RegB, getKillRegState(RegB)) in reassociateFMA()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 5697 Register RegB = AddMI->getOperand(IdxOpd1).getReg(); in genSubAdd2SubSub() local
5715 .addReg(RegB, getKillRegState(RegBIsKill)); in genSubAdd2SubSub()
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