125   bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
131   bool isProfitableToConv3Addr(Register RegA, Register RegB);
135                           Register RegB, unsigned &Dist);
436 static bool regsAreCompatible(Register RegA, Register RegB,  in regsAreCompatible()  argument
438   if (RegA == RegB)  in regsAreCompatible()
440   if (!RegA || !RegB)  in regsAreCompatible()
442   return TRI->regsOverlap(RegA, RegB);  in regsAreCompatible()
527                                                       Register RegB,  in isProfitableToCommute()  argument
567     MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);  in isProfitableToCommute()
595   if (!noUseAfterLastDef(RegB, Dist, LastDefB))  in isProfitableToCommute()
616   if (isRevCopyChain(RegB, RegA, MaxDataFlowEdge))  in isProfitableToCommute()
663                                                         Register RegB) {  in isProfitableToConv3Addr()  argument
670   MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);  in isProfitableToConv3Addr()
681     Register RegA, Register RegB, unsigned &Dist) {  in convertInstTo3Addr()  argument
717   DstRegMap.erase(RegB);  in convertInstTo3Addr()
1461   Register RegB = 0;  in processTiedPairs()  local
1472     RegB = MI->getOperand(SrcIdx).getReg();  in processTiedPairs()
1475     if (RegA == RegB) {  in processTiedPairs()
1484     assert(RegB.isVirtual() && "cannot make instruction into two-address form");  in processTiedPairs()
1501     MIB.addReg(RegB, 0, SubRegB);  in processTiedPairs()
1502     const TargetRegisterClass *RC = MRI->getRegClass(RegB);  in processTiedPairs()
1511         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))  in processTiedPairs()
1549     assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&  in processTiedPairs()
1557     if (RegA.isVirtual() && RegB.isVirtual())  in processTiedPairs()
1570       if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {  in processTiedPairs()
1586         LV->getVarInfo(RegB).removeKill(*MI)) {  in processTiedPairs()
1589       LV->addVirtualRegisterKilled(RegB, *PrevMI);  in processTiedPairs()
1593       SrcRegMap[LastCopiedReg] = RegB;  in processTiedPairs()
1610       LiveInterval &LI = LIS->getInterval(RegB);  in processTiedPairs()
1623       if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {  in processTiedPairs()
1643     Register RegB = TO.first;  in processStatepoint()  local
1655     assert(RegB == MI->getOperand(SrcIdx).getReg());  in processStatepoint()
1657     if (RegA == RegB)  in processStatepoint()
1660     MRI->replaceRegWith(RegA, RegB);  in processStatepoint()
1664       LiveInterval &LI = LIS->getInterval(RegB);  in processStatepoint()
1675         LV->removeVirtualRegisterKilled(RegB, *MI);  in processStatepoint()
1676       LiveVariables::VarInfo &SrcInfo = LV->getVarInfo(RegB);  in processStatepoint()
1680         LV->addVirtualRegisterKilled(RegB, *KillMI, false);  in processStatepoint()