| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 560 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() argument
561 return isSuperRegister(RegB, RegA); in isSubRegister()
565 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
568 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq() argument
569 return isSuperRegisterEq(RegB, RegA); in isSubRegisterEq()
574 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq() argument
575 return RegA == RegB || isSuperRegister(RegA, RegB); in isSuperRegisterEq()
580 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq() argument
581 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); in isSuperOrSubRegisterEq()
585 bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 438 if (RegA == RegB) in regsAreCompatible()
440 if (!RegA || !RegB) in regsAreCompatible()
654 SrcRegMap[RegA] = FromRegC; in commuteInstruction()
716 SrcRegMap.erase(RegA); in convertInstTo3Addr()
1475 if (RegA == RegB) { in processTiedPairs()
1482 LastCopiedReg = RegA; in processTiedPairs()
1504 if (RegA.isVirtual()) { in processTiedPairs()
1527 if (RegA.isVirtual()) { in processTiedPairs()
1559 MO.setReg(RegA); in processTiedPairs()
1657 if (RegA == RegB) in processStatepoint()
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| H A D | ImplicitNullChecks.cpp | 288 Register RegA = MOA.getReg(); in canReorder() local
295 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
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| H A D | TargetInstrInfo.cpp | 842 Register RegA = OpA.getReg(); in reassociateOps() local
848 if (Register::isVirtualRegister(RegA)) in reassociateOps()
849 MRI.constrainRegClass(RegA, RC); in reassociateOps()
878 .addReg(RegA, getKillRegState(KillA)) in reassociateOps()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86DynAllocaExpander.cpp | 226 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() local
228 .addReg(RegA, RegState::Undef); in lower()
240 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() local
242 .addReg(RegA, RegState::Undef); in lower()
254 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; in lower() local
255 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA) in lower()
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| H A D | X86RegisterInfo.cpp | 627 auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) { in isArgumentRegister() argument
628 return TRI.isSuperOrSubRegisterEq(RegA, RegB); in isArgumentRegister()
634 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }) || in isArgumentRegister() argument
644 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); })) in isArgumentRegister() argument
649 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); })) in isArgumentRegister() argument
656 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); })) in isArgumentRegister() argument
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| /llvm-project-15.0.7/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 126 bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const { in regsOverlap() argument
128 MCRegUnitIterator RUA(RegA, this); in regsOverlap()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 419 bool regsOverlap(Register RegA, Register RegB) const { in regsOverlap() argument
420 if (RegA == RegB) in regsOverlap()
422 if (RegA.isPhysical() && RegB.isPhysical()) in regsOverlap()
423 return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg()); in regsOverlap()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVModuleAnalysis.cpp | 200 Register RegA = A.getOperand(i).getReg(); in findSameInstrInMS() local
202 AllOpsMatch = MAI.getRegisterAlias(A.getMF(), RegA) == in findSameInstrInMS()
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| /llvm-project-15.0.7/llvm/unittests/Analysis/ |
| H A D | SparsePropagation.cpp | 479 auto RegA = TestLatticeKey(A, IPOGrouping::Register); in TEST_F() local
481 EXPECT_TRUE(Solver.getExistingValueState(RegA).isOverdefined()); in TEST_F()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2209 for (auto &RegA : DefsA) in isDependent() local
2212 if (RegA == RegB) in isDependent()
2215 if (Register::isPhysicalRegister(RegA)) in isDependent()
2216 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent()
2222 if (RegA == *SubRegs) in isDependent()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 5695 Register RegA = Root.getOperand(1).getReg(); in genSubAdd2SubSub() local
5701 Register NewVR = MRI.createVirtualRegister(MRI.getRegClass(RegA)); in genSubAdd2SubSub()
5714 .addReg(RegA, getKillRegState(RegAIsKill)) in genSubAdd2SubSub()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 527 Register RegA = Prev->getOperand(AddOpIdx).getReg(); in getFMAPatterns() local
528 MachineInstr *Leaf = MRI->getUniqueVRegDef(RegA); in getFMAPatterns()
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