125   bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
131   bool isProfitableToConv3Addr(Register RegA, Register RegB);
134                           MachineBasicBlock::iterator &nmi, Register RegA,
436 static bool regsAreCompatible(Register RegA, Register RegB,  in regsAreCompatible()  argument
438   if (RegA == RegB)  in regsAreCompatible()
440   if (!RegA || !RegB)  in regsAreCompatible()
442   return TRI->regsOverlap(RegA, RegB);  in regsAreCompatible()
526 bool TwoAddressInstructionPass::isProfitableToCommute(Register RegA,  in isProfitableToCommute()  argument
565   MCRegister ToRegA = getMappedReg(RegA, DstRegMap);  in isProfitableToCommute()
613   if (isRevCopyChain(RegC, RegA, MaxDataFlowEdge))  in isProfitableToCommute()
616   if (isRevCopyChain(RegB, RegA, MaxDataFlowEdge))  in isProfitableToCommute()
653     Register RegA = MI->getOperand(DstIdx).getReg();  in commuteInstruction()  local
654     SrcRegMap[RegA] = FromRegC;  in commuteInstruction()
662 bool TwoAddressInstructionPass::isProfitableToConv3Addr(Register RegA,  in isProfitableToConv3Addr()  argument
673   MCRegister ToRegA = getMappedReg(RegA, DstRegMap);  in isProfitableToConv3Addr()
681     Register RegA, Register RegB, unsigned &Dist) {  in convertInstTo3Addr()  argument
716   SrcRegMap.erase(RegA);  in convertInstTo3Addr()
1468     Register RegA = DstMO.getReg();  in processTiedPairs()  local
1475     if (RegA == RegB) {  in processTiedPairs()
1482     LastCopiedReg = RegA;  in processTiedPairs()
1493              MI->getOperand(i).getReg() != RegA);  in processTiedPairs()
1498                                       TII->get(TargetOpcode::COPY), RegA);  in processTiedPairs()
1504       if (RegA.isVirtual()) {  in processTiedPairs()
1505         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),  in processTiedPairs()
1511         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))  in processTiedPairs()
1527       if (RegA.isVirtual()) {  in processTiedPairs()
1528         LiveInterval &LI = LIS->getInterval(RegA);  in processTiedPairs()
1536         for (MCRegUnitIterator Unit(RegA, TRI); Unit.isValid(); ++Unit) {  in processTiedPairs()
1557     if (RegA.isVirtual() && RegB.isVirtual())  in processTiedPairs()
1558       MRI->constrainRegClass(RegA, RC);  in processTiedPairs()
1559     MO.setReg(RegA);  in processTiedPairs()
1653     Register RegA = DstMO.getReg();  in processStatepoint()  local
1657     if (RegA == RegB)  in processStatepoint()
1660     MRI->replaceRegWith(RegA, RegB);  in processStatepoint()
1665       for (auto &S : LIS->getInterval(RegA)) {  in processStatepoint()
1670       LIS->removeInterval(RegA);  in processStatepoint()
1677       LiveVariables::VarInfo &DstInfo = LV->getVarInfo(RegA);  in processStatepoint()