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Searched refs:Ra (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp159 unsigned Ra) { in addIntraChainConstraint() argument
160 if (Rd == Ra) in addIntraChainConstraint()
169 << Register::isPhysicalRegister(Ra) << '\n'); in addIntraChainConstraint()
187 const LiveInterval &la = LIs.getInterval(Ra); in addIntraChainConstraint()
243 unsigned Ra) { in addInterChainConstraint() argument
247 if (Chains.count(Ra)) { in addInterChainConstraint()
248 if (Rd != Ra) { in addInterChainConstraint()
251 Chains.remove(Ra); in addInterChainConstraint()
363 Register Ra = MI.getOperand(3).getReg(); in apply() local
365 if (addIntraChainConstraint(G, Rd, Ra)) in apply()
[all …]
H A DAArch64PBQPRegAlloc.h32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
H A DAArch64InstrInfo.td1853 GPR64:$Ra)),
4167 def : Pat<(f16 (fma (fneg FPR16:$Rn), FPR16:$Rm, FPR16:$Ra)),
4168 (FMSUBHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>;
4171 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
4174 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
4180 (FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>;
4183 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
4186 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
5265 V64:$Ra,
5273 V64:$Ra,
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H A DAArch64InstrFormats.td2263 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
2264 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
2268 bits<5> Ra;
2273 let Inst{14-10} = Ra;
2294 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
2315 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
5149 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
5150 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
5155 bits<5> Ra;
5160 let Inst{14-10} = Ra;
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp108 MCRegister Ra; in expandFunctionCall() local
111 Ra = RISCV::X6; in expandFunctionCall()
114 Ra = MI.getOperand(0).getReg(); in expandFunctionCall()
117 Ra = RISCV::X1; in expandFunctionCall()
120 Ra = MI.getOperand(0).getReg(); in expandFunctionCall()
129 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr); in expandFunctionCall()
136 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
139 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfast-isel-vararg.ll24 ; ARM: ldr [[Ra:r[0-9]+|lr]], [sp, #16]
27 ; ARM: str [[Ra]], [sp]
34 ; THUMB: ldr.w [[Ra:r[0-9]+]], [sp, #16]
36 ; THUMB: str.w [[Ra]], [sp]
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp90 Register Ra = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ() local
93 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(ARC::FLS_f_rr), Ra) in expandCTLZ()
98 .addReg(Ra); in expandCTLZ()
/llvm-project-15.0.7/
H A D.mailmap6 # "Rañdom Person" and sometimes "Random Person" as name and you want the former
9 # Rañdom Person <[email protected]>
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrInfo.td4040 "\t$Rd, $Rn, $Rm, $Ra",
4046 bits<4> Ra;
4050 let Inst{15-12} = Ra;
4327 bits<4> Ra;
4328 let Inst{15-12} = Ra;
4348 bits<4> Ra;
4350 let Inst{15-12} = Ra;
4531 [(set GPRnopc:$Rd, (add GPR:$Ra,
4555 [(set GPRnopc:$Rd, (add GPR:$Ra,
4632 bits<4> Ra;
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H A DARMInstrThumb2.td677 bits<4> Ra;
680 let Inst{15-12} = Ra;
2610 "usada8", "\t$Rd, $Rn, $Rm, $Ra",
2969 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2975 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3032 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3099 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3188 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
3200 (outs rGPR:$Ra, rGPR:$Rd),
5697 bits<4> Ra;
[all …]
H A DARMInstrFormats.td974 // MSW multiple w/ Ra operand
978 bits<4> Ra;
979 let Inst{15-12} = Ra;
1004 // AMulxyI with Ra operand
1008 bits<4> Ra;
1009 let Inst{15-12} = Ra;
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DBuiltins.def1061 LIBBUILTIN(vscanf, "icC*Ra", "fS:0:", "stdio.h", ALL_LANGUAGES)
1062 LIBBUILTIN(vfscanf, "iP*RcC*Ra", "fS:1:", "stdio.h", ALL_LANGUAGES)
1063 LIBBUILTIN(vsscanf, "icC*RcC*Ra", "fS:1:", "stdio.h", ALL_LANGUAGES)
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td885 def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt),
886 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>;
887 def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt),
888 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2742 unsigned Ra = fieldFromInstruction(Insn, 12, 4); in DecodeSMLAInstruction() local
2754 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) in DecodeSMLAInstruction()
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dbasic-a64-instructions.txt1095 # First check some non-canonical encodings where Ra is not 0b11111 (only umulh