Home
last modified time | relevance | path

Searched refs:RSP (Results 1 – 25 of 71) sorted by relevance

123

/llvm-project-15.0.7/lld/test/COFF/
H A Dlinkrepro.test17 # RUN: FileCheck %s --check-prefix=RSP < repro/response.txt
25 # RUN: FileCheck %s --check-prefix=RSP < repro2/response.txt
35 # RUN: FileCheck %s --check-prefix=RSP < repro/response.txt
73 # RSP: /subsystem:console
74 # RSP: /entry:main@0
75 # RSP: /out:
76 # RSP-NOT: /order:@/
77 # RSP-NOT: /def:/
78 # RSP: linkrepro.test.tmp.obj
79 # RSP-NOT: defaultlib
[all …]
H A Dlinkrepro-pdb.test17 RUN: cat repro/response.txt | FileCheck -check-prefix=RSP %s
23 RSP: -out:linkrepro-pdb.test.tmp.exe
24 RSP-NEXT: -pdb:linkrepro-pdb.test.tmp.pdb
25 RSP-NEXT: -nodefaultlib
26 RSP-NOT: -natvis:/
27 RSP-NOT: -pdbstream:srcsrv=/
H A Dlinkrepro-res.test10 # RUN: FileCheck %s --check-prefix=RSP < repro/response.txt
12 # RSP: resource.res
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/InstrRef/
H A Dderef-spills-with-size.mir32 # DW_OP_breg7 RSP-8, DW_OP_deref_size 0x8, DW_OP_stack_value
34 # DW_OP_breg7 RSP-8
36 # DW_OP_breg7 RSP-8, DW_OP_deref_size 0x1, DW_OP_stack_value
41 # DW_OP_breg7 RSP-8, DW_OP_piece 0x4
48 # DW_OP_breg7 RSP-8, DW_OP_deref_size 0x8, DW_OP_stack_value
50 # DW_OP_breg7 RSP-8, DW_OP_deref, DW_OP_stack_value
52 # DW_OP_breg7 RSP-8, DW_OP_deref_size 0x1, DW_OP_stack_value
78 # DWARF-NEXT: DW_OP_breg7 RSP-8, DW_OP_deref_size 0x1, DW_OP_stack_value
80 # DWARF-NEXT: DW_OP_breg7 RSP-8, DW_OP_deref_size 0x2, DW_OP_stack_value
83 # DWARF-NEXT: DW_OP_breg7 RSP-8
[all …]
/llvm-project-15.0.7/lld/test/ELF/
H A Dreproduce-error.s8 # RUN: tar xOf repro.tar repro/response.txt | FileCheck --check-prefix=RSP %s
9 # RSP: abc
10 # RSP: -o t
/llvm-project-15.0.7/lld/test/wasm/
H A Dreproduce.ll15 ; RUN: FileCheck --check-prefix=RSP %s < repro/response.txt
17 ; RSP: -o {{.*}}out.wasm
18 ; RSP: {{.*}}/foo.o
/llvm-project-15.0.7/llvm/test/MC/X86/
H A Dintel-syntax-2.s6 mov DWORD PTR [RSP - 4], 257
13 mov DWORD PTR [RSP - 4], 255
H A Dintel-syntax.s79 mov DWORD PTR [RSP - 4], 257
81 mov DWORD PTR [RSP + 4], 258
83 mov QWORD PTR [RSP - 16], 123
85 mov BYTE PTR [RSP - 17], 97
87 mov EAX, DWORD PTR [RSP - 4]
89 mov RAX, QWORD PTR [RSP]
93 mov DWORD PTR [RSP - 4], -4
97 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
H A Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dstatepoint-stackmap-format.ll190 ; Indirect Spill Slot [RSP+0]
218 ; Indirect Spill Slot [RSP+16]
225 ; Indirect Spill Slot [RSP+8]
232 ; Indirect Spill Slot [RSP+16]
239 ; Indirect Spill Slot [RSP+16]
277 ; Indirect Spill Slot [RSP+0]
305 ; Indirect Spill Slot [RSP+16]
312 ; Indirect Spill Slot [RSP+8]
319 ; Indirect Spill Slot [RSP+16]
326 ; Indirect Spill Slot [RSP+16]
[all …]
H A Ddbg-baseptr.ll11 ; Simple case: no FP, use offset from RSP.
25 ; DWARF: DW_AT_frame_base [DW_FORM_exprloc] (DW_OP_reg7 RSP)
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DFixupStatepointCallerSaved.cpp184 RegSlotPair RSP(Reg, FI); in recordReload() local
185 auto Res = Reloads[MBB].insert(RSP); in recordReload()
192 RegSlotPair RSP(Reg, FI); in hasReload() local
193 return Reloads.count(MBB) && Reloads[MBB].count(RSP); in hasReload()
246 for (auto &RSP : GlobalIndices[EHPad]) in reset() local
247 ReservedSlots.insert(RSP.second); in reset()
257 Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; }); in getFrameIndex() argument
/llvm-project-15.0.7/llvm/test/MC/AsmParser/
H A Ddirective_seh.s69 sub RSP, 24
72 mov [16+RSP], RSI
77 movups [RSP], XMM8
/llvm-project-15.0.7/bolt/test/X86/
H A Dshrinkwrapping-and-rsp.s2 # using RSP when the function is aligning RSP and changing offsets.
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DTargetTest.cpp84 ElementsAre(IsReg(X86::RSP), IsImm(1), IsReg(0), IsImm(Offset), in IsMovValueToStack()
90 ElementsAre(IsReg(Reg), IsReg(X86::RSP), IsImm(1), IsReg(0), in IsMovValueFromStack()
96 ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size))); in IsStackAllocate()
101 ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size))); in IsStackDeallocate()
/llvm-project-15.0.7/llvm/test/tools/llvm-dwarfdump/X86/
H A Ddebug_loclists.s30 # REGULAR-NEXT: [0x0000000000000007, 0x0000000000000008): DW_OP_reg7 RSP
31 # VERBOSE-NEXT: [0x0000000000000007, 0x0000000000000008) ".text": DW_OP_reg7 RSP
59 # REGULAR-NEXT: [0x0000000000000007, 0x0000000000000008): DW_OP_reg7 RSP
61 # VERBOSE-NEXT: => [0x0000000000000007, 0x0000000000000008) ".text": DW_OP_reg7 RSP
/llvm-project-15.0.7/llvm/test/DebugInfo/X86/
H A Dasan_debug_info.ll15 ; [0x000000000000006d, 0x00000000000000a4): DW_OP_breg7 RSP+16, DW_OP_deref, DW_OP_plus_uc…
16 ; [0x00000000000000a6, 0x00000000000000ef): DW_OP_breg7 RSP+16, DW_OP_deref, DW_OP_plus_uc…
31 ; CHECK-NEXT: DW_AT_location (DW_OP_breg7 RSP+32, DW_OP_plus_uconst 0x20)
H A Ddbg-addr-dse.ll61 ; DWARF-NEXT: {{[^:]*}}: DW_OP_breg7 RSP+{{[0-9]+}}
63 ; DWARF-NEXT: {{[^:]*}}: DW_OP_breg7 RSP+{{[0-9]+}})
H A Dfission-ranges.ll50 ; CHECK-NEXT: DW_LLE_startx_length (0x00000003, 0x00000012): DW_OP_breg7 RSP-4
54 ; CHECK-NEXT: DW_LLE_startx_length (0x00000005, 0x0000005a): DW_OP_breg7 RSP-36
58 ; CHECK-NEXT: DW_LLE_startx_length (0x00000007, 0x00000042): DW_OP_breg7 RSP-24
62 ; CHECK-NEXT: DW_LLE_startx_length (0x00000009, 0x0000002a): DW_OP_breg7 RSP-12
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp461 .addReg(X86::RSP) in allocateStackSpace()
462 .addReg(X86::RSP) in allocateStackSpace()
471 .addReg(X86::RSP) // BaseReg in fillStackSpace()
485 .addReg(X86::RSP) // BaseReg in loadToReg()
495 .addReg(X86::RSP) in releaseStackSpace()
496 .addReg(X86::RSP) in releaseStackSpace()
547 .addReg(X86::RSP) // BaseReg in loadX87STAndFinalize()
563 .addReg(X86::RSP) // BaseReg in loadX87FPAndFinalize()
584 .addReg(X86::RSP) // BaseReg in loadImplicitRegAndFinalize()
/llvm-project-15.0.7/lld/test/COFF/Inputs/
H A Dpdb-scopes-a.yaml56 Register: RSP
96 Register: RSP
107 Register: RSP
120 Register: RSP
H A Dpdb-scopes-b.yaml56 Register: RSP
67 Register: RSP
80 Register: RSP
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp262 {codeview::RegisterId::RSP, X86::RSP}, in initLLVMToSEHAndCVRegMapping()
453 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; in createX86MCAsmInfo()
755 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
783 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
820 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
856 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
892 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
893 return X86::RSP; in getX86SubSuperRegisterOrZero()
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCPlusBuilder.cpp1045 StackPtrReg = X86::RSP; in isStackAccess()
1067 StackPtrReg = X86::RSP; in isStackAccess()
1378 static BitVector SPAliases(getAliases(X86::RSP)); in escapesVariable()
2389 Inst.addOperand(MCOperand::createReg(X86::RSP)); in createStackPointerIncrement()
2390 Inst.addOperand(MCOperand::createReg(X86::RSP)); in createStackPointerIncrement()
2410 Inst.addOperand(MCOperand::createReg(X86::RSP)); in createStackPointerDecrement()
2411 Inst.addOperand(MCOperand::createReg(X86::RSP)); in createStackPointerDecrement()
3250 static BitVector SPAliases(getAliases(X86::RSP)); in createInstrumentedIndirectCall()
3320 createSwap(Insts[3], TempReg, X86::RSP, 0); in createInstrumentedIndCallHandlerExitBB()
3321 createIndirectBranch(Insts[4], X86::RSP, -8); in createInstrumentedIndCallHandlerExitBB()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td176 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
431 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
433 // GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
463 R8, R9, R11, RIP, RSP)>;
466 RIP, RSP)>;
484 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
489 // GR64_NOSP - GR64 registers except RSP (and RIP).
490 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
497 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.

123