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Searched refs:ROR (Results 1 – 25 of 42) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td16 /// ROL [~] ROR [~] ROXL [ ] ROXR [ ]
98 defm ROR : MxSROp<"ror", rotr, MxRODI_R, MxROOP_RO>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h38 ROR, enumerator
59 case AArch64_AM::ROR: return "ror"; in getShiftExtendName()
80 case 3: return AArch64_AM::ROR; in getShiftType()
108 case AArch64_AM::ROR: STEnc = 3; break; in getShifterImm()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedPredExynos.td140 // Identify EXTR as the alias for ROR (immediate).
H A DAArch64SchedPredicates.td51 def CheckShiftROR : CheckImmOperand_s<3, "AArch64_AM::ROR">;
H A DAArch64SchedAmpere1.td990 (instregex "(ASR|LSL|LSR|ROR)V(W|X)r")>;
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/
H A Dm7-int.s364 sxtab r0, r1, r2, ROR #8
366 sxtab16 r0, r1, r2, ROR #8
368 sxtah r0, r1, r2, ROR #8
371 sxtb.w r0, r1, ROR #8
373 sxtb16 r0, r1, ROR #8
376 sxth.w r0, r1, ROR #8
416 uxtab r0, r1, r2, ROR #8
420 uxtah r0, r1, r2, ROR #8
423 uxtb.w r0, r1, ROR #8
425 uxtb16 r0, r1, ROR #8
[all …]
H A Dm4-int.s373 sxtab r0, r1, r2, ROR #8
375 sxtab16 r0, r1, r2, ROR #8
377 sxtah r0, r1, r2, ROR #8
380 sxtb.w r0, r1, ROR #8
382 sxtb16 r0, r1, ROR #8
385 sxth.w r0, r1, ROR #8
429 uxtab r0, r1, r2, ROR #8
433 uxtah r0, r1, r2, ROR #8
436 uxtb.w r0, r1, ROR #8
438 uxtb16 r0, r1, ROR #8
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.h50 ROR, ///< Bit rotate right. enumerator
H A DAVRISelLowering.cpp250 NODE(ROR); in getTargetNodeName()
323 Opc8 = AVRISD::ROR; in LowerShifts()
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h181 static inline uint32_t ROR(const uint32_t value, const uint32_t amount, in ROR() function
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dthumb1.txt354 # ROR
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb2-diagnostics.s52 @ Out of range immediate for ROR.
H A Dbasic-thumb-instructions.s484 @ ROR
H A Dthumb2-narrow-dp.ll654 // ROR
660 ROR r5, r1, r5 // Must use wide encoding as not flag-setting
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h555 ROR, enumerator
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1752 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRRtPCRelative()
6357 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRImmediateARM()
6496 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRRegister()
8346 rotated = ROR(R[m], rotation); in EmulateSXTB()
8401 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateSXTB()
8431 rotated = ROR(R[m], rotation); in EmulateSXTH()
8486 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateSXTH()
8516 rotated = ROR(R[m], rotation); in EmulateUXTB()
8571 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateUXTB()
8599 rotated = ROR(R[m], rotation); in EmulateUXTH()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SchedSandyBridge.td989 "ROR(8|16|32|64)m(1|i)")>;
1034 "ROR(8|16|32|64)mCL",
H A DX86SchedSkylakeClient.td1202 "ROR(8|16|32|64)m(1|i)")>;
1285 "ROR(8|16|32|64)mCL",
H A DX86SchedBroadwell.td1137 "ROR(8|16|32|64)m(1|i)")>;
1214 "ROR(8|16|32|64)mCL",
H A DX86ScheduleAtom.td515 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
H A DX86SchedHaswell.td1215 "ROR(8|16|32|64)m(1|i)")>;
1359 "ROR(8|16|32|64)mCL",
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM7.td338 def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)")>;
H A DARMScheduleSwift.td154 // ASR,LSL,ROR,RRX
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1337 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR || in isShifter()
1443 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) && in isLogicalShifter()
3201 .Case("ror", AArch64_AM::ROR) in tryParseOptionalShiftExtend()
3223 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZb.td367 def ROR : ALU_rr<0b0110000, 0b101, "ror">,
826 def : PatGprGpr<shiftop<rotr>, ROR>;

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