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Searched refs:ROL (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td16 /// ROL [~] ROR [~] ROXL [ ] ROXR [ ]
97 defm ROL : MxSROp<"rol", rotl, MxRODI_L, MxROOP_RO>;
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.h51 ROL, ///< Bit rotate left. enumerator
H A DAVRISelLowering.cpp249 NODE(ROL); in getTargetNodeName()
319 Opc8 = AVRISD::ROL; in LowerShifts()
H A DAVRInstrInfo.td60 def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>;
2110 def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8 : $rd, GPR8 : $rd)>;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SchedSandyBridge.td988 def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)",
1033 def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL",
H A DX86SchedSkylakeClient.td1201 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
1284 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
H A DX86SchedBroadwell.td1136 def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
1213 def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
H A DX86ScheduleAtom.td515 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
H A DX86SchedHaswell.td1214 def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",
1358 def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",
H A DX86InstrCompiler.td1850 // ROL/ROR instructions allow a stronger mask optimization than shift for 8- and
1879 defm : MaskedRotateAmountPats<rotl, "ROL">;
2228 // register-register 16 bit bswap. This maps it to a ROL instruction.
H A DX86SchedSkylakeServer.td1470 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1641 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
H A DX86SchedIceLake.td1484 def: InstRW<[ICXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1660 def: InstRW<[ICXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
H A DX86InstrInfo.td3678 defm : ShiftRotateByOneAlias<"rol", "ROL">;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZb.td365 def ROL : ALU_rr<0b0110000, 0b001, "rol">,
825 def : PatGprGpr<shiftop<rotl>, ROL>;
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2576 case Mips::ROL: in tryExpandInstruction()
4875 if (Inst.getOpcode() == Mips::ROL) { in expandRotation()
4893 case Mips::ROL: in expandRotation()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.td2529 def ROL : MipsAsmPseudoInst<(outs),
2536 (ROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
/llvm-project-15.0.7/clang-tools-extra/clang-tidy/misc/ConfusableTable/
H A Dconfusables.txt555 …* ( ᰼ → ᰻᰻ ) LEPCHA PUNCTUATION NYET THYOOM TA-ROL → LEPCHA PUNCTUATION TA-ROL, LEPCHA PUNCTUATION…