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Searched refs:RL (Results 1 – 25 of 60) sorted by relevance

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/llvm-project-15.0.7/llvm/unittests/Remarks/
H A DRemarksLinkingTest.cpp18 static void serializeAndCheck(remarks::RemarkLinker &RL, in serializeAndCheck() argument
26 Error E = RL.serialize(OS, OutputFormat); in serializeAndCheck()
45 remarks::RemarkLinker RL; in check() local
46 EXPECT_FALSE(RL.link(Input, InputFormat)); in check()
47 serializeAndCheck(RL, OutputFormat, ExpectedOutput); in check()
53 remarks::RemarkLinker RL; in check() local
54 EXPECT_FALSE(RL.link(Input, InputFormat)); in check()
55 EXPECT_FALSE(RL.link(Input2, InputFormat2)); in check()
194 remarks::RemarkLinker RL; in TEST() local
208 RL.setExternalFilePrependPath("/baddir/"); in TEST()
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H A DYAMLRemarksParsingTest.cpp418 const remarks::RemarkLocation &RL = *Remark.Loc; in TEST() local
420 EXPECT_EQ(RL.SourceLine, 3U); in TEST()
421 EXPECT_EQ(RL.SourceColumn, 12U); in TEST()
443 const remarks::RemarkLocation &RL = *Arg.Loc; in TEST() local
445 EXPECT_EQ(RL.SourceLine, 2U); in TEST()
446 EXPECT_EQ(RL.SourceColumn, 0U); in TEST()
590 const remarks::RemarkLocation &RL = *Remark.Loc; in TEST() local
592 EXPECT_EQ(RL.SourceLine, 3U); in TEST()
593 EXPECT_EQ(RL.SourceColumn, 12U); in TEST()
617 EXPECT_EQ(RL.SourceLine, 2U); in TEST()
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H A DBitstreamRemarksParsingTest.cpp176 const remarks::RemarkLocation &RL = *Remark.Loc; in TEST() local
177 EXPECT_EQ(checkStr(RL.SourceFilePath, 6), "file.c"); in TEST()
178 EXPECT_EQ(RL.SourceLine, 3U); in TEST()
179 EXPECT_EQ(RL.SourceColumn, 12U); in TEST()
201 const remarks::RemarkLocation &RL = *Arg.Loc; in TEST() local
202 EXPECT_EQ(checkStr(RL.SourceFilePath, 6), "file.c"); in TEST()
203 EXPECT_EQ(RL.SourceLine, 2U); in TEST()
204 EXPECT_EQ(RL.SourceColumn, 0U); in TEST()
/llvm-project-15.0.7/compiler-rt/test/tsan/
H A Ddeadlock_detector_stress_test.cpp290 RL(2); RL(3); RU(2); RU(3); in Test8()
291 RL(3); RL(2); RU(2); RU(3); in Test8()
374 RL(000); in Test12_Thread()
375 RL(100); in Test12_Thread()
376 RL(200); in Test12_Thread()
377 RL(300); in Test12_Thread()
397 RL(0); in Test13_Thread()
398 RL(100); in Test13_Thread()
400 RL(200); in Test13_Thread()
402 RL(300); in Test13_Thread()
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/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Checkers/
H A DPaddingChecker.cpp91 const ASTRecordLayout &RL = ASTContext.getASTRecordLayout(RD); in visitRecord() local
92 assert(llvm::isPowerOf2_64(RL.getAlignment().getQuantity())); in visitRecord()
94 CharUnits BaselinePad = calculateBaselinePad(RD, ASTContext, RL); in visitRecord()
101 calculateOptimalPad(RD, ASTContext, RL); in visitRecord()
192 const ASTRecordLayout &RL) { in calculateBaselinePad() argument
194 CharUnits Offset = ASTContext.toCharUnitsFromBits(RL.getFieldOffset(0)); in calculateBaselinePad()
206 auto FieldOffsetBits = RL.getFieldOffset(FD->getFieldIndex()); in calculateBaselinePad()
211 PaddingSum += RL.getSize() - Offset; in calculateBaselinePad()
233 const ASTRecordLayout &RL) { in calculateOptimalPad() argument
271 CharUnits NewOffset = ASTContext.toCharUnitsFromBits(RL.getFieldOffset(0)); in calculateOptimalPad()
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H A DRunLoopAutoreleaseLeakChecker.cpp100 const auto *RL = Match.getNodeAs<ObjCMessageExpr>(RunLoopBind); in emitDiagnostics() local
124 (RL ? "main run loop " : "xpc_main ") + in emitDiagnostics()
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
15 store i64 %tmp1617, i64* %RL
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
34 store i64 %tmp1617, i64* %RL
/llvm-project-15.0.7/llvm/lib/Remarks/
H A DYAMLRemarkSerializer.cpp25 Optional<RemarkLocation> RL, T FunctionName, in mapRemarkHeader() argument
30 io.mapOptional("DebugLoc", RL); in mapRemarkHeader()
77 static void mapping(IO &io, RemarkLocation &RL) { in mapping()
80 StringRef File = RL.SourceFilePath; in mapping()
81 unsigned Line = RL.SourceLine; in mapping()
82 unsigned Col = RL.SourceColumn; in mapping()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBlockRanges.cpp75 void HexagonBlockRanges::RangeList::include(const RangeList &RL) { in include() argument
76 for (auto &R : RL) in include()
442 RangeList &RL = F->second; in computeDeadMap() local
443 RangeList::iterator A = RL.begin(), Z = RL.end()-1; in computeDeadMap()
514 const HexagonBlockRanges::RangeList &RL) { in operator <<() argument
515 for (auto &R : RL) in operator <<()
532 const HexagonBlockRanges::RangeList &RL = I.second; in operator <<() local
533 OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; in operator <<()
H A DHexagonBlockRanges.h117 void include(const RangeList &RL);
241 const HexagonBlockRanges::RangeList &RL);
H A DHexagonFrameLowering.cpp2343 RL.add(LastStore[FI], LastLoad[FI], false, false); in optimizeSpillSlots()
2345 RL.add(IndexType::Entry, LastLoad[FI], false, false); in optimizeSpillSlots()
2358 auto &RL = FIRangeMap[I.first].Map[&B]; in optimizeSpillSlots() local
2361 RL.add(LS, LL, false, false); in optimizeSpillSlots()
2363 RL.add(IndexType::Entry, LL, false, false); in optimizeSpillSlots()
2370 auto &RL = FIRangeMap[I.first].Map[&B]; in optimizeSpillSlots() local
2371 RL.add(LS, IndexType::None, false, false); in optimizeSpillSlots()
2448 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B]; in optimizeSpillSlots() local
2449 for (auto &Range : RL) { in optimizeSpillSlots()
2450 LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n'); in optimizeSpillSlots()
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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmisched-fusion-addr.ll59 ; CHECK: adrp [[RL:x[0-9]+]], var_64bit
60 ; CHECK-NEXT: str {{x[0-9]+}}, [[[RL]], {{#?}}:lo12:var_64bit]
71 ; CHECK: adrp [[RL:x[0-9]+]], var_64bit
72 ; CHECK-NEXT: ldr {{x[0-9]+}}, [[[RL]], {{#?}}:lo12:var_64bit]
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGRecordLayoutBuilder.cpp905 auto RL = std::make_unique<CGRecordLayout>( in ComputeRecordLayout() local
909 RL->NonVirtualBases.swap(Builder.NonVirtualBases); in ComputeRecordLayout()
910 RL->CompleteObjectVirtualBases.swap(Builder.VirtualBases); in ComputeRecordLayout()
913 RL->FieldInfo.swap(Builder.Fields); in ComputeRecordLayout()
916 RL->BitFields.swap(Builder.BitFields); in ComputeRecordLayout()
924 RL->print(llvm::outs()); in ComputeRecordLayout()
947 llvm::StructType *ST = RL->getLLVMType(); in ComputeRecordLayout()
962 unsigned FieldNo = RL->getLLVMFieldNo(FD); in ComputeRecordLayout()
972 const CGBitFieldInfo &Info = RL->getBitFieldInfo(FD); in ComputeRecordLayout()
973 llvm::Type *ElementTy = ST->getTypeAtIndex(RL->getLLVMFieldNo(FD)); in ComputeRecordLayout()
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/llvm-project-15.0.7/llvm/tools/dsymutil/
H A DDwarfLinkerForBinary.cpp231 StringRef ArchName, const remarks::RemarkLinker &RL) { in emitRemarks() argument
234 if (RL.empty()) in emitRemarks()
262 if (Error E = RL.serialize(OS, Options.RemarksFormat)) in emitRemarks()
271 remarks::RemarkLinker &RL) { in loadObject() argument
285 Error E = RL.link(*ErrorOrObj); in loadObject()
564 remarks::RemarkLinker RL; in link() local
566 RL.setExternalFilePrependPath(Options.RemarksPrependPath); in link()
595 [&DebugMap, &RL, this](StringRef ContainerName, in link()
600 if (auto ErrorOrObj = loadObject(Obj, DebugMap, RL)) { in link()
705 if (auto ErrorOrObj = loadObject(*Obj, Map, RL)) in link()
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H A DDwarfLinkerForBinary.h203 remarks::RemarkLinker &RL);
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp510 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_Select() local
514 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_Select()
544 Lo = DAG.getNode(Opcode, dl, LL.getValueType(), CL, LL, RL); in SplitRes_Select()
553 Lo = DAG.getNode(Opcode, dl, LL.getValueType(), CL, LL, RL, EVLLo); in SplitRes_Select()
559 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
562 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
565 N->getOperand(1), LL, RL, N->getOperand(4)); in SplitRes_SELECT_CC()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp410 auto RL = Reg2Local.find(Reg); in runOnMachineFunction() local
411 if (RL == Reg2Local.end() || RL->second < MFI.getParams().size()) in runOnMachineFunction()
414 MFI.setLocal(RL->second - MFI.getParams().size(), in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.td39 def RL#i : NVPTXReg<"%rd"#i>; // 64-bit
62 def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 4), VRFrame64, VRFrameLocal64)>;
/llvm-project-15.0.7/llvm/include/llvm/ADT/
H A DImmutableSet.h510 TreeTy *RL = getLeft(R);
513 if (getHeight(RR) >= getHeight(RL))
514 return createNode(createNode(L,V,RL), R, RR);
516 assert(!isEmpty(RL) && "RL cannot be empty because it has a height >= 1");
518 TreeTy *RLL = getLeft(RL);
519 TreeTy *RLR = getRight(RL);
521 return createNode(createNode(L,V,RLL), RL, createNode(RLR,R,RR));
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ196.td176 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
177 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
192 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
194 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
220 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
222 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
271 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LA(Y|RL)?$")>;
487 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
504 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
546 def : InstRW<[WLat1, LSU, GroupAlone], (instregex "PFD(RL)?$")>;
[all …]
H A DSystemZScheduleZEC12.td181 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
182 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
200 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
202 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
228 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
230 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
282 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LA(Y|RL)?$")>;
498 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
515 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
556 def : InstRW<[WLat1, LSU, NormalGr], (instregex "PFD(RL)?$")>;
[all …]
H A DSystemZScheduleZ13.td197 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
220 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
222 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
251 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
253 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
308 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LA(Y|RL)?$")>;
526 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
543 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
584 def : InstRW<[WLat1, LSU, NormalGr], (instregex "PFD(RL)?$")>;
[all …]
H A DSystemZScheduleZ16.td199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
222 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
224 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
256 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
258 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
313 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LA(Y|RL)?$")>;
550 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
567 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
608 def : InstRW<[WLat1, LSU, NormalGr], (instregex "PFD(RL)?$")>;
[all …]
H A DSystemZScheduleZ15.td199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
222 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
224 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
256 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
258 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
313 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LA(Y|RL)?$")>;
550 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
567 def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
608 def : InstRW<[WLat1, LSU, NormalGr], (instregex "PFD(RL)?$")>;
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dextract_vector_dynelt.ll85 ; GCN: s_lshr_b64 s[[[RL:[0-9]+]]:{{[0-9]+}}], s[[[SL]]:[[SH]]], [[SEL]]
86 ; GCN-DAG: v_mov_b32_e32 v[[VRL:[0-9]+]], s[[RL]]
349 ; GCN: s_lshr_b64 s[[[RL:[0-9]+]]:{{[0-9]+}}], s[[[SL]]:[[SH]]], [[SEL]]
350 ; GCN-DAG: v_mov_b32_e32 v[[VRL:[0-9]+]], s[[RL]]

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